|Publication: EE Times Memory Designline|
Contributor: Memoir Systems, Inc.
July 30, 2012 -- In the age of broadband Internet, 4G smart phones, and untethered tablet computing, there is a relentless demand for ever-increasing computing performance. Over the years, processing performance has rapidly progressed, initially via increasing clock speeds and then later courtesy of architectural innovations such as instruction-level parallelism, pipelining, and the issuing of multiple instructions per cycle. Memory performance, on the other hand, has not kept pace, thus creating the traditional processor-memory gap.
Despite attempts to temper that gap with huge increases in on-chip memory capacity and the advent of multicore architectures (once again increasing the effective processing performance), system-on-chip (SOC) architects and designers continue to struggle to meet the performance requirements of today's data-hungry applications. Memory technology is long overdue for an innovation that can increase performance by an order of magnitude. One promising technology, algorithmic memory, combines existing embedded memories with the capabilities of algorithms to increase embedded memory performance by a factor of 10. While not a panacea, it offers a new and innovative approach to alleviating the disparity between processor and memory performance in SOCs.
By Sundar Iyer. (Iyer is co-founder and CTO at Memoir Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Memory Designline website.
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Memoir Systems, Inc.
|Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, embedded memory, Memoir Systems, EE Times Memory Designline|
|602/38979 7/30/2012 693 61|