| Configurable Dividers for SOC/ Block-Level Clocking by Freescale Semiconductor, Inc. in EE Times EDA Designline |
September 4, 2012 -- Clocking constitutes one of the most important aspect of block- or SOC-level design and its architecture needs to well-defined and understood during the conceptualizing/ planning phase of the design. In a single SOC there ar ... read more |
| 6 Reasons You Should Customize Your DSP Cores by Tensilica, Inc. in Chip Estimate Corp. |
September 1, 2012 -- There are plenty of good, proven DSP IP cores on the market today. Many designs use a standard 32-bit processor coupled with a separate DSP core to accelerate digital signal processing. However, using two processors means th ... read more |
| Get Better Emulation Results in Less Time by Emulation and Verification Engineering (EVE) in Electronic Design Magazine |
August 31, 2012 -- The telescope atop Mauna Kea is precious and rare. Astronomers sign up for it long in advance. When their allocated time window comes, they have to make the most of it because, when it's over, it's over. Someone else's window ... read more |
| Non-Invasive Techniques Advance Electrical Tests by GOEPEL electronic GmbH in EE Times Test & Measurement Designline |
August 28, 2012 -- Testing electronic circuits has been an important topic in the industry since the first transistor was developed, and today it is as relevant as ever. However, we do have certain requirements that should be met by our test sol ... read more |
| ADC Basics-Part 1: Does Your ADC Work in the Real World? by Texas Instruments, Inc. (TI) in EE Times Planet Analog |
August 27, 2012 -- Real-world environmental occurrences such as temperature, pressure, flow or light usually require a specialized sensor to adequately capture an ecological status or change. Although sensors can convert these physical occurrenc ... read more |
| Layer-Aware Optimization by Synopsys, Inc. in EE Times EDA Designline |
August 27, 2012 -- At advanced technology nodes, longer wire lengths and highly resistive metal layers have led to a dramatic increase in interconnect delays. Traditional buffering and up-sizing techniques to reduce interconnect delay are no lon ... read more |
| Successful PCB Grounding with Mixed-signal Chips-Part 1: Principles of Current Flow by Maxim Integrated Products, Inc. in EDN Magazine |
August 27, 2012 -- Board-level designers often have concerns about the proper way to handle grounding for integrated circuits which have separate analog and digital grounds. Should the two be completely separate and never touch? Should they conn ... read more |
| Verifying Embedded Software Functionality-Part 3: Fault Localization, Metrics and Directed Testing by EE Times Embedded |
August 26, 2012 -- This third part in a four part series discusses the pros and cons of metric-base fault localization and directed testing for assessing software functionality. Part 1 and Part 2 in this series presented the dynamic-s ... read more |
| Growing Audio Requirements in SOCs by Synopsys, Inc. in EE Times Audio Designline |
August 23, 2012 -- As consumer devices such as tablets, media players and home-theater systems continue to incorporate more audio functionality, the systems-on-chip (SOCs) designed for these devices become more complex. These SOCs must support a ... read more |
| Design Workflow Management Enhances SOC Design Quality and Efficiency by Global UniChip Corp. in EE Times EDA Designline |
August 20, 2012 -- Every semiconductor company and for that matter, every technology company, constantly juggles a number of designs that are at different stages of development. To handle the numerous challenges, semiconductor companies in parti ... read more |
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