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 Category: SOCcentral Feature Articles & Columns: Barbaras Bytes: Friday, October 31, 2014
MEMS Growth Calls for Market, Manufacturing Changes   Featured
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December 3, 2012 -- With MEMS having become central to consumer products such as smart phones and tablets, the exploding demand for them makes it imperative for designers to focus on product, not process technology. Toward that goal, the MEMS industry is coming to terms with a huge shift in manufacturing methodology, one that is moving the MEMS market toward accessible and cost-effective process technology. Traditionally, IDMs have been the only ones with resources needed to develop the specialized, proprietary processes that have characterized MEMS manufacture. But the long R&D cycles and build-and-test design required for such an approach are no longer viable now that MEMS technology lies at the heart of consumer products with short product life-cycles. The high-volume, cost-driven consumer market calls for more standardized processes, packaging and testing.

Today's demand to produce innovative, competitive products calls for collaboration among pure-play foundries, MEMS makers and EDA design companies. Potential MEMS makers with novel ideas but no fabrication resources need to partner with foundries to access standardized MEMS processes, packaging and testing. At the same time, MEMS makers and foundries need to work with EDA companies to develop virtual fabrication tools, process design kits (PDKs) and tool sets that encompass the design of MEMS and analog and mixed-signal ASICs that provide control circuitry for MEMS products. With foundry and EDA support, designers should be able to cut the cost of MEMS/ ASIC manufacture, keep up with demand for short product life-cycles and ramp to volume production.

Fabless model gains favor

With its embrace of the fabless model, motion-tracking MEMS maker InvenSense keeps costs low by leveraging TSMC's and GlobalFoundries' standard CMOS processes and equipment and guarantees capacity to customers. Combining MEMS and CMOS wafers enables InvenSense to reduce manufacturing steps, and integrating multiple sensors on a single die alleviates the necessity to duplicate I/O and packaging, reports Steve Lloyd, Vice President of Engineering and Product Development. "InvenSense fabricates both MEMS and CMOS in the same flow, with bonded MEMS on CMOS wafers intimately connected, says Lloyd. "We're promoting an SOC approach to MEMS. That's where the industry has to go."

As for tools, MEMS makers have no access to fully integrated tool sets and need to mix and match third-party and in-house tools, says Lloyd. But EDA vendors are pushing the integration level of their tool sets. At the system-level, tools are tightly integrated, he claims, but at the manufacturing level, there are still two families of separate tools.

Rakesh Patel, MEMS Director at GlobalFoundries exclaims, "Development cost and time of MEMS is directly proportional to degree of customization required in the manufacturing process. Foundries can cut time and cost by offering standardized process modules and using them for manufacturing to the maximum possible extent."

Integration complexity involved in MEMS design materials, fabrication, testing and IP have been behind IDMs being the dominant suppliers of MEMS, says Patel. "Considered a core competency, MEMS manufacturing know-how has been mostly kept a trade secret by IDMs. As MEMS manufacturing becomes mainstream, fabless companies will find market opportunities by developing products that are high performing and use cost-effective manufacturing."

Patel also believes that with shorter and shorter product life-cycles, a fabless model can help MEMS makers respond faster to market needs and to concentrate efforts on novel designs, developing complete product/ application solutions. As for integration with control circuitry, "A mainstream 8-inch ASIC process offers a reliable solution for MEMS ASIC in a cost-effective and timely manner. It allows companies to focus their efforts on their sensor solution rather than worrying about issues that relate to ASIC manufacturing or functionality," he says.

Patel points to the significance of virtual manufacturing tools that can identify potential issues before the start of process development. A challenge for the emerging high-volume MEMS industry based on a fabless model is that there is no industry roadmap for MEMS product specifications. "There is large variability and lack of clarity on system-level specifications using MEMS," he cautions. "MEMS being formed by 3D structures will require the development of 3D modeling/ simulation tools for optimized design performance. But the availability of standard process modules will help in accelerating the design of MEMS." Patel also emphasizes the importance of foundries and EDA tool providers working together to develop process-design kits (PDKs).

A PDK, according to Stephen Breit, Vice President of Engineering at Coventor, should include a description of the layers in the MEMS process: stacking order, material, nominal thickness and thickness statistics. Next, PDKs need to provide material properties of the MEMS layers, including at least mechanical, electrical and thermal properties plus fabrication-induced, pre-stress distributions in MEMS layers. Also required is a layout template, containing at least the expected GDS layers. The PDK, too, should include design-rule checks (DRCs): minimum feature size, minimum spacing between features, etc.

Open fabrication platforms

To make MEMS design more accessible, InvenSense has opened up its Nasiri fabrication (NF) silicon CMOS-MEMS platform to emerging MEMS developers on a limited licensing basis. With NF-Shuttle, multiple developers split mask costs and purchase "seats" on the same mask, enabling MEMS makers with creative design ideas but few resources to reduce production costs and verify prototypes in silicon. The company's next NF-Shuttle service is scheduled for this December, 2012. Researchers at Stanford, UC Berkeley and others have taken advantage of this approach for the design and production of inertial sensors and resonators, microphones, switches, pressure sensors and RF tuners.

X-FAB Semiconductor Foundries AG, another foundry active in MEMS manufacture, sees the use of a mainstream CMOS process for MEMS + ASIC design as a key requirement going forward. X-FAB manufactures MEMS on 6-inch and 8-inch wafers to cut cost in high volumes. "There is a distinct requirement for some MEMS devices to be integrated with or on top of CMOS technology for signal processing and other smart sensor applications," says Iain Rutherford, X-FAB's MEMS Product Marketing Manager. "We definitely take an SOC approach to our foundry service," he adds.

X-FAB leverages synergies between CMOS and MEMS processes to optimize cost and increase yield. For example, customers can use CMOS to design an ASIC and add one mask layer to turn that into a CMOS-integrated pressure sensor. The analog/ mixed-signal CMOS used with sensors is advancing from 1-m to 0.35-m to 0.18-m design rules, and X-FAB is using these technologies to provide discrete ASICs and integrated MEMS.

X-FAB offers engineering services and early access prototyping for its open-platform MEMS 3-D inertial sensor process, with full qualification and complete design rule access expected early next year. "We work closely with our customers on their product development for processing and manufacturability," says Rutherford. X-FAB's modular process system provides an understanding of how various structures such as membranes, bridges, inertial masses and channels can be formed, supporting customer-specific process transfer and development. X-FAB's design rules and DRC for MEMS processes accelerate development and permit customers to perfect designs before committing them to silicon. The foundry also offers finite-element analysis (FEA) and virtual wafer-processing capabilities.

EDA tackles tools issues

As fabless MEMS companies with good design ideas gain access to CMOS-MEMS processes from foundries, the next issue is the level of support offered by EDA companies. One issue is MEMS IP libraries. "We're pretty far away from that for patent reasons and because all structures are optimized for a particular process," says Coventor's Breit. Nevertheless, he believes that the IP market for MEMS will have to happen. Some providers, however, already tout IP libraries for MEMS.

The debate, says Juan Rey, Engineering Director of R&D for Mentor Graphics Corp's' Design to Silicon Division, is over what level of IP or predefined MEMS components is useful. "If you create a complete device, like a sensor or motor or other actuator, it may not be applicable across different applications," Rey explains. "But suppliers are providing libraries of more basic components like micro gears, motor armatures and other components that can be modified to work together in a larger assembly."

For many companies, X-FAB's Rutherford says that their competitive advantage lies in their design, but he believes the ubiquity of MEMS in the future, and the concentration of volume production on a limited number of MEMS types, will make it advantageous to give customers access to IP blocks and libraries.

An outstanding issue is to bridge the gap between multi-physics-based MEMS and traditional IC design, claims Coventor's Breit. Also to be tackled are the MEMS-specific challenge of electro-mechanical coupling and the lack of automation between hand-off and verification.

As for LVS for MEMS, X-FAB's Rutherford says he doesn't believe a simple "model" for a general MEMS structure actually exists today. "An integration into an analog/ mixed-signal design flow as a primitive device seems rather unlikely. The MEMS component needs to be treated as a box or block structure. It also may be very dependent upon the function of a MEMS component because a membrane for a pressure sensor is completely different from a comb or finger structure of seismic masses for an accelerometer or gyroscope. X-FAB is working on standardizing such components." X-FAB is offering different ready-to-use IP blocks with models for simulating circuitry using black-box principles and inserting the proven layouts into customer designs.

Design tools are incrementally improving over time. Coventor's MEMS+ tool set has just been enhanced (MEMS+ 3.0) to include an enlarged MEMS component library and new fluidic simulation capabilities including gas dumping for sensors and actuators and pressure loads for microphones. The aim of adding fluidics to the existing mechanical- and electrostatic-modeling capabilities is to enable fully coupled simulations that will predict performance metrics such as noise or actuation time which until now required costly build-and-test cycles. Coventor's aim is to compress each stage of the design cycle with simulation. Toward that end, the company has integrated MATLAB and Simulink from the MathWorks, Inc. and the Virtuoso custom IC design solution from Cadence Design Systems, Inc. into its tool set to enable MEMS+ users to simulate the complex physics of MEMS devices together with IC circuits and control systems.

Figure 1. Coventor has integrated MATLAB, Simulink and Cadence Virtuoso into its MEMS+ tool set.

The packaging-effects analysis that's part of MEMS+ 3.0 is expected to be relevant to coupling effects in instances where MEMS and ASICs are intimately connected by wafer bonding, notes Coventor's Breit. "The thermal cycling during the fabrication process and the operating environment could cause stress and deformation in the MEMS die, which could in turn affect performance of the MEMS, and these effects can be modeled with MEMS+ 3.0."

The cross-parasitics between MEMS and ASIC can be addressed with Coventor's Analyzer tool, suggests Breit, and also with traditional parasitic-extraction tools such as Mentor's Calibre. Mentor also has physical-verification tools to check that a MEMS device meets physical (foundry) design rules and to verify proper connectivity of the electronics that drives a MEMS device.

Coventor is collaborating with foundries to provide PDKs that include process-emulation files that work with Coventor's products, somewhat analogous to Cadence tech files, reports Breit. The PDKs also include a material-properties database plus a layout template for Coventor's layout editor with DRCs and a design handbook.

Through a partnership with Belgian nanoelectronics research organization IMEC, Coventor is developing PDKs that target IMEC's SiGe MEMS technology and its approach to process the MEMS after and on top of the CMOS for a monolithic integration of MEMS devices with driving and readout electronics on the same die. Also, as part of the MEMS2015 project, Coventor is working with X-FAB to develop PDKs for inertial sensors built with an X-FAB process. X-FAB was one of the first customers for Coventor's SEMulator3D virtual-fabrication tool for MEMS layout verification prior to tape-out. Although Mentor has not announced any turnkey PDKs for MEMS foundries, it's working with many current and future MEMS suppliers to understand and meet their EDA requirements.

MEMS maker MEMSIC chooses to use Tanner EDA tools to integrate its thermo-mechanical sensors with analog/ mixed-signal processing on silicon using a standard CMOS process. For its latest accelerometers, MEMSIC designers add MEMS Pro from SoftMEMS to Tanner's tool set. Designers use MEMS Pro for 3D mechanical-model extraction for finite-element analysis. They use Tanner's L-Edit to modify details of the sensor and to do layout and pattern list plus LVS and DRC. They then export from L-Edit to a GDS layout file and send that to TSMC for tape-out.

Clearly, industry players are making progress in the MEMS space, but will it be enough to meet demand as the MEMS industry is predicted by Yole to become a $21 billion global market by 2017? Beyond consumer applications, MEMS are finding their way into wearable health monitors, climate monitoring, oil exploration and production, smart highway infrastructure and tsunami/ earthquake warning. Such expectations should, indeed, motivate industry players to simplify MEMS manufacture and make tools accessible. To do so, it's essential to further standardize MEMS processes, put PDKs into the hands of designers, integrate MEMS/ ASIC design tool sets, enhance modeling /simulation technology and develop MEMS IP component libraries.

By Barbara Tuck.

Barbara Tuck is SOCcentral.com's Senior Editor for SOC design and all things related to EDA, ASICs and FPGAs, and IP. In addition to her work with SOCcentral, she is available for freelance assignments and can be reached by phone at 843-972-8051 or by e-mail at Barbara_Tuck@SOCcentral.com.


Keywords: ASICs, ASIC design, microelectromechanical systems, micro-electro-mechanical systems, MEMS, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, SOCcentral,
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