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 Category: News: News Archive 2013: Wednesday, October 01, 2014
Cadence Introduces the Tempus Timing Sign-off Solution  
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May 20, 2013 -- In a move to ease and speed the development of complex ICs, Cadence Design Systems, Inc. today introduced the Tempus Timing Sign-off Solution, a new static timing-analysis and -closure tool designed to enable system-on-chip (SOC) developers to speed timing closure and move chip designs to fabrication quickly. The Tempus Timing Sign-off Solution represents a new approach to timing sign-off tools that enables designers to shrink timing sign-off closure and analysis for faster tape-out while producing designs with less pessimism, area and power consumption.

The new capabilities introduced in the Tempus Timing Sign-off Solution include:

  • A massively distributed parallel timing engine which can scale to utilize up to hundreds of CPUs.
  • Parallel architecture enables the Tempus Timing Sign-off Solution to analyze designs in the hundreds of millions of instances without compromising accuracy.
  • A new path-based analysis engine that leverages multi-core processing to reduce pessimism. The Tempus Timing Signoff Solution enables broader use of path-based analysis than other solutions.
  • Multi-mode, multi-corner (MMMC) analysis and physically-aware timing closure that leverages multi-threaded and distributed timing analysis.

"Today, the time spent in timing closure and sign-off is approaching 40 percent of the overall design implementation flow. Traditional sign-off flows have failed to keep pace with the increasing demands of achieving timing closure on complex designs," observed Anirudh Devgan, Corporate Vice President, Silicon Sign-off and Verification, Silicon Realization Group at Cadence. "The Tempus Timing Sign-off Solution represents a significant advancement in timing sign-off tool innovation and performance, leveraging multi-processing and ECO features to achieve sign-off faster than with traditional flows."

Availability

The Tempus Timing Sign-off Solution is expected to be available in the third quarter of 2013.

Cadence plans to showcase the tool's advanced capabilities at DAC, June 3-5, 2013 in Austin, Texas.

Posted by: John Miklosz



Go to the Cadence Design Systems, Inc. website to find additional information.

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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, timing analysis, timing optimization, timing closure, Cadence Design Systems, Tempus Timing Sign-off
608/40593 5/20/2013 1568 142
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