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Survey Shines Light on the State of ESL Design   Featured
Contributor: Mentor Graphics Corp.
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May 8, 2006 -- In the world of electronics, new design methodologies are often slow to reach mainstream acceptance. In general, engineers do not adopt new methodologies until design challenges become exceedingly difficult and eventually breaking the established methodology. In the hardware domain, we've seen illustrations of this concept in the transition from schematic capture to GDSII and eventually to RTL. Now with a new generation of devices in development, we are seeing yet another transition, this time to Electronic System Level (ESL) design.

The reason is simple; design complexity. Even if you take into account the growing reliance on intellectual property (IP) reuse and platform-based design, Gartner Dataquest estimates that 30% of the gates in next-generation designs will still need to be specified and verified. That amounts to roughly 15 million gates in a 50-million-gate 9-nm ASIC design. Hand-coding a 15-million-gate design with register-transfer level (RTL) methodologies is a long, complex task which increasingly leads to sub-optimal designs, functional errors, and/or extended design times. With larger, more complex applications in the works, designers need tools and methodologies to dramatically increase productivity, provide relief from complexity, and reduce design time.

ESL design tools can help designers manage these millions of gates but ESL is a broad term, and many in the electronics industry are unclear about what it is and how it can help.

To gauge industry perceptions and adoption trends in ESL design, Mentor Graphics conducted a survey of over 1200 electronics professionals across Europe. The Mentor Graphics European ESL Survey asked about current and former applications, design problems, perceptions and experience with ESL design methodologies. We found widespread experience of the kinds of difficulties that ESL design promises to relieve. We also found interesting data on why some engineers have adopted ESL, why some have not, what it will take to adopt ESL methodologies and when those who haven't adopted believe they will do so.

ESL's killer app

When asked which of the design tasks in their existing methodology could be improved, survey respondents gravitated to issues surrounding system modeling and verification, most commonly citing increased simulation speed and ability to do HW/SW co-verification. We could deduce from this that respondents want to create virtual system prototypes that simulate at adequate speed to enable early software validation, system performance analysis and overall superior system architectures. And indeed, when asked which design tasks were necessary for an effective ESL methodology, system modeling topped the list again.

These responses align nicely with the EDA industry's marketing messages about ESL, many of which focus on high-level modeling and early assessment. Since only 24% of respondents have implemented ESL methodologies prior to the survey, it would be reasonable to attribute some of this tidy alignment to the influence of marketing on those who do not yet have direct experience of ESL. Validation of the alignment will come when ESL tool sales start to rise more sharply.

Common threads of ESL users

Among the respondents who have used ESL methodologies, an overwhelming majority say ESL methodologies provide an acceptable or greater return on investment. This statistic obviously bodes well for the future of ESL design. As more designers begin to encounter problems with complexity, they will need assurances that ESL methodologies and tools are mature and deliver on their many promises. With a growing record of successful implementations, it appears ESL design tools have satisfied questions of maturity and reliability, and are poised for further growth among mainstream designers.

In fact, respondents who already use ESL tools cite risk reduction as a top reason for adopting the new methodologies. This is particularly true of ESL synthesis, as automation reduces the number of errors introduced during hand coding of a design. The traditional design flow uses a process of "progressive refinement" in which one starts with a high abstraction source (typically C/C++) and manually refines the high-level description into lower and lower abstraction models until finally one achieves a model which can be synthesized into hardware. But each transformation introduces errors and each error must be found, fixed and then re-verified. While these hand-coded errors were acceptable when designs were smaller, the number of bugs increases proportionally with the number of gates in silicon, creating a verification burden that is growing as fast as complexity.

In addition, high abstraction ESL models allow system designers to build virtual prototypes, allowing them to fully validate their system and explore different architectures with minimal effort. This early visibility into performance and functionality allows designers to find an optimal design rather settle for the sub-optimal, which reduces the risk of functional failures and re-design later in the design cycle.

Non-users speak

When non-users of ESL tools were asked why they had not adopted the new methodologies, nearly one third said that their designs are not complex enough to warrant ESL methodologies (i.e. existing RTL methodologies suffice). However, the majority (57%) of this same group of non-users predict that within the next three years design complexity will escalate to a point that will require ESL technology solutions.

The survey report examines ESL design trends in greater detail, revealing insights on implementation trends, barriers to adoption, specifics on which design tasks are most needed, and data on language preferences in ESL. To sign up to receive the entire report, go to European ESL Survey.

By Shawn McCloud. (McCloud is the High-Level Synthesis Product Line Director for Mentor Graphics Corp.)

Go to the Mentor Graphics Corp. website to learn more.

Keywords: SOCcentral, Mentor Graphics, electronic system level design, ESL,
488/18920 5/8/2006 11369 11369
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