January 14, 2008 -- This article describes a new approach for chip design and system-level integration. A hierarchical RTL context-preserving insertion and connectivity methodology has been further implemented in EDA tool – chip IP integrator. This article shares the approach, methodology and the results on a real-life system comprising several RTL design blocks in Verilog each having around a quarter of million instances as well as on an ARM 4 CPU test chip design. The tool maintains two dynamic views – design tree view and parse tree view which allow for hierarchical insertion, accounting for design reuse and preserving shared module connectivity as well as input design context.
By Mikhail Baklashov. (Baklashov is with ARM, Inc., USA)
This brief introduction has been excerpted from the original copyrighted article.