October 22, 2009 -- The design of a Network-on-Chip (NoC) requires the use of simulation tools to characterize its performance metrics. However, cycle-accurate models are time-costly and the simulation of a large system can consume several hours of computing. The evaluation time can be significantly reduced by running the performance evaluation experiments on a NoC implemented directly on hardware, typically using FPGA. In this article, there are presented synthesizable cores for a traffic generator and a traffic meter developed to be used in a platform for performance evaluation of NoCs in FPGA. These cores were implemented as single-purpose processors and allow a fast performance evaluation of a NoC.
By Thiago Felski Pereira and Cesar Albenes Zeferino. (Pereira and Zeferino are with Univali.)
This brief introduction has been excerpted from the original copyrighted article.