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Guidelines for Complex SOC Verification  
Publication: EE Times EDA Designline
Contributor: eInfochips, Ltd.
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February 15, 2010 -- Almost 60 to 70% of time in the ASIC cycle is occupied by functional verification and so, the main aim of this article is to provide overall guidelines in verification. More specifically, on the adoption of various planning strategies, managing the dynamics in projects and a metric-driven execution approach with the maximum possible automation and reusability that helps deliver a quality product on time and achieve silicon success.

Consider the example of a typical SOC, consisting of a processor, several IPs, direct memory access for data control, a common bus matrix for data transfers and inter-block communication and a system memory for data storage. The requirements may change many times during the execution of a project. For instance, system memory size may be changed from X to Y to meet software needs. Third-party IP may need to be changed, or a new IP or feature may need to be added. So, significant SoC functional specification change happens and we have to deal with adding, changing and removing features targeted for verification, updates in register definition and the like.

With the above dynamics, a verification team has to tackle the following hurdles:

  • How to or what to plan in verification.
  • What type of execution flow model needs to be setup.
  • How to manage SOC verification on time.

By Jignesh Oza. (Oza is with eInfochips, Ltd.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the EE Times EDA Designline website.

Read more about
eInfochips, Ltd.

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, verification, system-on-chip, SoC, EE Times EDA Designline, eInfochips,
596/30792 2/15/2010 6290 383
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