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Get the Lowdown on Accellera's VIP and UVM  
Publication: Chip Design Magazine
Contributor: Accellera
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April 1, 2011 -- Many of you are probably wondering what's happening with Accellera's Universal Verification Methodology (UVM) effort, which debuted its Early Adopter (EA) release in May of last year. We're very close to a release that's currently set for the first part of this year. The most significant aspect of this release is that it includes all of the major features requested by the verification community. Among them are two new features built by the committee: a command-line interface and resource manager. We also fully qualified the EA features and dispensed with almost all of the bugs and enhancement requests.

The UVM 1.0 release includes a new phasing mechanism and register package. It also supports the Open SystemC Initiative's (OSCI's) Transaction Level Modeling- 2.0 (TLM-2.0) standard. It includes a command-line interface as well as an upgrade to its configuration mechanism (or resource manager) to make it more general. Added features include callbacks, message catching, and functionality in the objection mechanism for managing end of test.

By Thomas Alsop. (Alsop is with Intel Corp. and is Co-chair of Accellera's VIP and UVM Committees.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Chip Design Magazine website.

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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, verification IP, intellectual property, cores, SystemC, transaction level modeling, transaction-level modeling, TLM, Universal Verification Methodology, UVM, Accellera, Chip Design Magazine,
599/33669 4/1/2011 1997 144


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