Page loading . . .

 You are at: The item(s) you requested.Sunday, April 19, 2015
Cavium Networks Licenses Arteris FlexNoC Network on Chip Interconnect IP  
 Printer friendly
 E-Mail Item URL

July 12, 2011 -- Arteris SA today announced that it has entered into an agreement with Cavium Networks, Inc. to provide Arteris' FlexNoC network-on-chip interconnect fabric IP.

"Arteris' NoC interconnect technology is often called, 'a front-end solution to a back-end problem,' because using Arteris IP simplifies the front-end design process while easing back-end wire-routing congestion and timing-closure issues," said Farhad Mighani, Senior Director of ASIC Development at Cavium Networks.

"Cavium's purchase of Arteris' FlexNoC network-on-chip IP and memory scheduler products after a thorough technical evaluation demonstrates Arteris' capability to deliver the best-performing and most-scalable interconnect solution to SOC designers," said K. Charles Janac, President and CEO of Arteris.

Go to the Arteris SA website to find additional information.

E-mail Arteris SA for more information.

Read more about
Arteris SA
Cavium, Inc.

Keywords: ASICs, ASIC design, IP, intellectual property, cores, on-chip interconnect, network-on-chip, NoC, Arteris FlexNoC, Cavium Networks,
600/34247 7/12/2011 942 121
Designer's Mall

Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

P2415: The New Power Standard for Unified Hardware Abstraction

Graham Bell
VP Marketing
Real Intent

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.53125