Page loading . . .

 You are at: The item(s) you requested.Friday, September 30, 2016
Snowbush IP Group Launches New Multi-Standard PHY IP Platform on TSMC 28-nm Process  
 Printer friendly
 E-Mail Item URL

July 12, 2011 -- Snowbush IP Group today announced the availability of its third generation of silicon-proven Multi-Standard (MS) PHY IP Platform on TSMC 28-nm technology. The new platform, which is capable of supporting a number of different high-speed serial standards, includes a number of architectural changes to improve performance while adjusting to the design challenges of the 28-nm node. The new MS PHY, operates at speeds up to 12.5Gbps and at 7.2mW per Gbps per channel in a quad configuration.

Support for multiple standards

The Snowbush MS PHY IP operates at speeds ranging from 1Gbps to over 12Gbps. Supported standards include Ethernet for 10GBase-KR, BASE-R, XFI, RXAUI and XAUI; Optical Interface Forum (OIF) for CEI-11G and CEI6G; PCI-SIG for PCIe 3,2, and 1; USB 3.0; SATA and SAS at 1.5Gbps, 3Gbps and 6Gbps, and is positioned to handle the new emerging SATA standards at 12Gbps The new MS PHY features new digital control for programming the SerDes to support different standards. Digital calibration and trimming tune the performance of the PHY and adaptation functionality adjusts to varied channel characteristics to ensure the best quality of service on the link. Auto-negotiation and link training are provided for standards requiring those features.

In addition to exceeding the performance requirements of the targeted standards, the new Snowbush MS PHY is highly programmable and optimized for low power and minimal silicon footprint. The low-power transmit driver is immune to supply noise while delivering amplitude and slew rate programmability as well as multi-tap pre- and post-emphasis.

On the receive side, a continuous time-linear equalizer (CTLE) with automatic gain control (AGC) feeds a 5-tap decision feedback equalizer (DFE) to minimize inter-symbol interference (ISI) and deliver optimized eye data. The MS PHY supports a number of different power-management modes including allowing each lane to be powered-down independently.

A number of test and debug features are available including an on-chip EyeView-Scope-on-a-Chip eye monitor for accurate visibility of the input signal quality and performance of the equalization, pseudo random bit sequence (PRBS) generators/ checkers with a user-defined-pattern option, and jitter injection. AC JTAG is also available.


The MS PHY (Part #SBMULT550T28HP11G) is available now for instantiation on SOC designs.

Go to the Snowbush IP Group website to find additional information.

E-mail Snowbush IP Group for more information.

Read more about
Snowbush IP Group
TSMC (Taiwan Semiconductor Manufacturing Company)

Keywords: ASICs, ASIC design, PHY IP, intellectual property, cores, Snowbush IP Group, TSMC (Taiwan Semiconductor Manufacturing Company)
600/34257 7/12/2011 882 156
Designer's Mall

Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  2.71875