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Duolog Announces Socrates Bitwise 1.11.0 Product Release  
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July 18, 2011 -- Duolog Technologies has announced the latest release of its tool. Bitwise manages the HW/SW register, memory-map and interface definitions for IPs, subsystems or SOCs and provides a single-source specification for register and memory-map information. Bitwise is a fully interoperable solution that supports current and emerging standards such as TLM2.0, IP-XACT and UVM.

Bitwise 1.11.0 Release features include:
  • IP-XACT 1.5 (IEEE1685-2009) import and export.
  • UVM 1.0 register package generator.
  • Auto-generation of OpenCores I2C slave interface.
  • Bus/ abstraction definition linking.
  • Python and Perl generator support.
  • ARM Cortex CMSIS (device.h) generator.
  • Excel and CSV import and CSV generation.


Go to the Duolog Technologies website to find additional information.

E-mail Duolog Technologies for more information.

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Duolog Technologies
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Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, Duolog Technologies, Socrates Bitwise register management, IP, intellectual property, cores, system-on-chip, SoC,
600/34290 7/18/2011 836 147
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