Page loading . . .

  
 You are at: The item(s) you requested.Monday, December 22, 2014
Cognovo Software Defined Baseband Chip Released to Samsung Foundry 450nm Low-Power Process  
 Printer friendly
 E-Mail Item URL

July 21, 2011 -- Cognovo, Ltd. builds momentum with the successful tape-out of a software defined modem (SDM) device in Samsung Foundry's advanced 45-nm LP (low power) process. The device, based on Cognovo's latest MCE160 Modem Compute Engine IP core, will enable licensees to develop soft modems in all cellular and wireless standards including WiFi, 2G, 3G, HSPA+, LTE and LTEAdvanced.

Built around Cognovo's Vector Signal Processor (VSP) technology, spun out of ARM in 2009, the synthesisable MCE160 core delivers a record 250GOps (Giga Operations per second) processing power. The performance achieved is sufficient to allow UE (User Equipment) modems to be created in software for many wireless standards, including LTE-Advanced, or for other algorithmically intensive applications such as cellular infrastructure.

A development platform incorporating the baseband device will be available, and will be supported by Cognovo's Soft Modem Integrated Development Environment. The combination of a full-system software development and modeling methodology with real-time hardware for real-world validation lets Cognovo's licensees complete their Soft Modem development in parallel with the creation of production silicon.

Cognovo's Software Defined Modem Development Kit (SDM-SDK) consists of an optimizing compiler, code profiler and a real-time multi-processor design and modeling environment that lets licensees easily migrate existing hardware-centric designs to the flexible Cognovo platform. Since the platform is capable of supporting current and future wireless standards, modem evolution can be rapidly carried out in software.

"The industry has been waiting for a credible approach to SDM for many years and Cognovo is delivering a low-power, wireless-optimized architecture," commented Ian Drew, Executive Vice President of Marketing, ARM. "Harnessing this through a multicore system, including ARM Cortex processors and Physical IP, with an integrated tool chain to address design, modeling and validation will make the silicon from Samsung's advanced process an exciting proof point."

"We are already working with companies to exploit our MCE120 product in the 3G LTE market," said Gordon Aspin, CEO at Cognovo. "However, by providing the MCE160-based development platform, together with our SDM Software Development Kit, we will allow companies to create the first modem prototypes for LTE-A as soon as next year."

Cognovo's SDM platform comprises the Modem Compute Engine (MCE); a licensable processor sub-system available in a number of configurations, the SDM Operating System (SDMOS) and a fully Integrated Development Environment for SDM creation and validation.

Availability

Samples will be available to lead customers later this year.

Go to the Cognovo, Ltd. website to find additional information.

E-mail Cognovo, Ltd. for more information.

Read more about
Cognovo, Ltd.
on SOCcentral.com


Keywords: ASICs, ASIC design, embedded system design, embedded systems, IP, intellectual property, cores, ARM-based microprocessors, Cortex MPUs, DSP, digital signal processing, digital signal processors, software defined modem, SDM, Cognovo,
600/34342 7/21/2011 726 101
Designer's Mall

0.453125



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Verification Contortions


Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Executive
Viewpoint

Deep Semantic and Formal Analysis


Dr. Pranav Ashar
CTO, Real Intent

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.515625