October 12, 2011 -- United Microelectronics Corp. (UMC) and Synopsys, Inc. today announced an expanded collaboration to develop DesignWare IP for UMC's 28-nm HLP Poly SiON process. Extending its previous successes in UMC's 40-nm and 55-nm processes, Synopsys plans to implement its proven DesignWare embedded memories and logic libraries in UMC's 28HLP Poly SiON process technology. This collaboration will let designers create high-speed, low-power system-on-chips (SOCs) with less risk and improved time-to-market. The longstanding relationship between the two companies extends the availability of high-quality DesignWare IP for a wide range of UMC processes from 180nm to 28nm.

While preserving the cost-competitiveness of conventional Poly SiON gate stack and using proprietary process techniques, UMC's 28HLP process technology delivers exceptional performance-to-cost ratio with improved performance and power consumption over other 28-nm Poly SiON offerings. This enhanced 28-nm Poly-SiON process provides a natural migration path from 40-nm, enabling easy design adoption and fast time-

The DesignWare embedded memories and logic libraries supporting UMC's 28HLP process are scheduled to be available in Q2 2012. The 28HLP DesignWare embedded memories and logic libraries will be available at no cost to qualified licensees as part of Synopsys' Foundry Sponsored IP program.