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Vivante and Cadence Unveil Mass-Market GPU-Optimized DDR Memory Solution  
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March 14, 2012 -- Vivante Corp. today announced that it has worked with Cadence Design Systems, Inc. to qualify the Cadence double data rate (DDR) Memory controller intellectual property (IP) solution for use with Vivante's graphics processing unit (GPU) IP solution.

Vivante's high-performance multicore GPUs are capable of processing massive amounts of data in order to create the most advanced and realistic 3D visual effects on mobile, embedded and home entertainment devices. To render high-quality images, the GPU requires access to external DDR DRAM through a highly optimized, low-latency DDR memory controller.

The collaboration between Cadence and Vivante has created a tightly coupled memory subsystem that maximizes the efficiency between the GPU, memory controller and external DDR memory. Vivante's memory-friendly architecture uses design features such as burst building, request merging, efficient data access, compression, prefetching, smart banking, prediction and much more. These features provide the optimal data flow and memory-access patterns for graphics applications. The Cadence DDR controller works as the interface between the GPU and DDR memory, fine-tuned to perform data and traffic management. This co-optimized solution enables SOC designers to select a proven, performance-enhanced solution ready for mass market deployment.

"Consumer markets that use our GPUs, such as smartphones, tablets and HDTVs, are already visually aware. These segments are upping the ante for better graphics, augmented reality, flashy images, and captivating game play based on our new GPU cores. Balancing performance and memory bottlenecks is a key enabler to achieving these new experience levels," said Wei-Jin Dai, President and CEO of Vivante. "Our collaboration with Cadence was the key focus to innovate and build the ideal graphics memory system. As these technologies are built into our memory-friendly designs already, we have solutions that benefit from the bandwidth, power, size and cost equations SOC architects have to account for."

Go to the Cadence Design Systems, Inc. website to find additional information.

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Keywords: ASICs, ASIC design, IP, intellectual property, cores, embedded memory, DDR memory, graphics processors, graphics processing units, GPUs, Vivante, Cadence Design Systems,
601/38081 3/14/2012 444 68


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