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Arasan Chip Systems Announces MIPI-Compliant Low-Latency Interface (LLI) IP Solution  
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May 2, 2012 -- Arasan Chip Systems, Inc. announced today the availability of its MIPI LLI controller IP along with a matching Type 1 M-PHY, the latest additions to its MIPI portfolio.

Both the applications processors and the baseband processors for mobile platforms are complex SOCs. Although the two chips are often integrated into one SOC by a number of chip vendors, a number of high-end mobile chipsets are still split into two separate processors. They each have their own system-level memory to allow efficient cache refills. LLI is a chip-to-chip link layer interconnect protocol that allows efficient, low-latency cache refills from the DRAM associated with a companion chip, thereby removing the need for two separate sets of DRAMs and substantially reducing the cost of mobile platforms. LLI requires M-PHY Type 1 as the physical layer.

Arasan has developed a combined LLI controller and M-PHY Type 1 solution, which can be configured for a variety of host buses (such as AHB, AXI and OCP), and bandwidth/ latency requirements across multiple traffic classes. Using up to six lanes of M-PHY’s this solution offers up to 17 Gbps bandwidth in each direction, with only one clock domain crossing in the LLI controller. Designers are given a choice of either source-synchronous or independent clocking in the M-PHYs for clock- and data-recovery mechanisms in the analog receivers.

Arasan is ready to engage with users starting at an architectural-consulting level, all the way through the delivery of a properly configured LLI controller RTL and M-PHY macro. As with all other Arasan IP, these are delivered with accompanying verification IP and several other scripts and files required for successful integration into each companion chip.

Availability

Arasan's MIPI LLI Controller IP Core is available immediately for licensing, including Verilog HDL of the IP Core, verification IP, synthesis scripts, and documentation. The corresponding M-PHY IP is available as a hard macro targeted to any process node, along with all the required support files and documentation.



Go to the Arasan Chip Systems, Inc. website to find additional information.

E-mail Arasan Chip Systems, Inc. for more information.

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Arasan Chip Systems, Inc.
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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, MIPI-Compliant Low-Latency Interface, Arasan Chip Systems,
601/38361 5/2/2012 479 63


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