SOCcentral: Lessons in Developing and Deploying OVM-Compliant VIP (Design & Reuse 38448)

You are at: The item(s) you requested.

Thursday, May 23, 2013

Lessons in Developing and Deploying OVM-Compliant VIP Featured

Publication: Design & Reuse
Contributor: Test and Verification Solutions, Ltd. (TVS)

Printer friendly

E-Mail Item URL

May 3, 2012 -- Using external VIP (verification IP) brings several advantages including availability, independence in both checkers and coverage, and robustness from use in several environments. However, the VIP must be developed so that it is easy for the user to incorporate the VIP into his/her environment. In this article we look at practical lessons learned in both the development and deployment of VIP for use in complex OVM (Open Verification Methodology) SOC (system-on-chip) verification environments.

By Mike Bartley and Andy Bond. (Bartley is with Test and Verification Solutions and Bond is Lead Verification Engineer for Icera.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the Design & Reuse website.

Read more about
Test and Verification Solutions, Ltd. (TVS)
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, verification IP, intellectual property, cores, Open Verification Methodology, OVM, Design & Reuse, Test and Verification Solutions

602/38448 5/3/2012 895 80

Designer's Mall

0.15625

Search site for:
Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification

Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP

Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!

Mike Donlin
The Write Solution
Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL

Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search
SOC Design ASIC Design ASIC Verification FPGA Design CPLD Design PCB Design DSP Design RTOS Development Digital Design	Analog Design Mixed-Signal Design DFT DFM IC Packaging VHDL Verilog SystemC SystemVerilog