| The Next Roadblock to Custom-Design Productivity: Design Constraints Featured |
May 21, 2013 -- Design constraints, which express design intent, are one of the pieces of ancillary data that are critical to the success or failure of a custom design. Design constraints aren't usually contained within layout files or library in ... read more |
| Category: SOCcentral Feature Articles & Columns: Feature Articles: |
| Mentor and Tezzaron Optimize Calibre 3DStack for 2.5/3D-ICs |
May 20, 2013 -- Mentor Graphics Corp. and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor Calibre 3DStack product into Tezzaron's 3D-IC offerings. The new integration will focus ... read more |
| Category: News: News Archive 2013: |
| sureCore, Ltd. |
sureCore, Ltd. is a semiconductor IP company focusing on low-power physical IP for next-generation silicon process technologies. sureCore is developing low-power and variability-tolerant design techniques that are applicable to a wide range of IP ... read more |
| Category: Vendors, Organizations & Universities: Vendors: |
| Aldec Launches Spec-TRACER Requirements Lifecycle Management for Safety-critical FPGA and ASIC Designs |
May 20, 2013 -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for FPGA and ASIC devices, today announced the launch of Spec-TRACER™, a new requirements lifecycle management solution for use in safety-critica ... read more |
| Category: News: News Archive 2013: |
| Ausdia Receives Patent for System and Method for Automatically Managing Clock Relationships in IC Designs |
May 20, 2013 -- Ausdia, Inc. has been issued patent number US 8,438,517 B2 by the United States Patent and Trademark Office. The patent discloses automated techniques for identifying and managing the relationship between clock domains in ... read more |
| Category: News: News Archive 2013: |
| Cadence Introduces the Tempus Timing Sign-off Solution |
May 20, 2013 -- In a move to ease and speed the development of complex ICs, Cadence Design Systems, Inc. today introduced the Tempus Timing Sign-off Solution, a new static timing-analysis and -closure tool designed to enable system-on-chip ... read more |
| Category: News: News Archive 2013: |
| Fourth Multicore Challenge Now Open for Registration |
May 20, 2013 -- Taking place in Bristol UK on June 12, this year the conference, sponsored by Test and Verification Solutions, Ltd. (TVS), will focus on heterogeneous systems with three main themes of heterogeneous architectures, low power ... read more |
| Category: News: News Archive 2013: |
| QuickLogic Parallel Camera Interface for TI Sitara AM335x ARM Cortex-A8 Processors Supports Android Jelly Bean 4.1.2 OS |
May 20, 2013 -- QuickLogic Corp. today announced that its Parallel Camera Interface (CAM I/F) for Sitara AM335x ARM Cortex-A8 processors from Texas Instruments, Inc. (TI) now supports the Android Jelly Bean 4.1.2 Operating System (O ... read more |
| Category: News: News Archive 2013: |
| Synopsys DesignWare IP for PCI Express 3.0 Passes First PCI-SIG PCIe 3.0 Compliance Workshop |
May 20, 2013 -- Synopsys, Inc. has announced that its DesignWare PHY and digital controller IP for the PCI-SIG PCI Express 3.0 is the first complete solution from a single vendor to pass compliance testing at the first PCI-SIG compliance w ... read more |
| Category: News: News Archive 2013: |
| Xilinx Achieves PCI Express Compliance Across Its All Programmable 28-nm Devices |
May 20, 2013 -- Xilinx, Inc. today announced that its All Programmable 7 series FPGAs and Zynq-7000 All Programmable SoCs have achieved full PCI Express compliance and are now listed on the PCI-SIG integrator's list. All of Xilinx's 28-nm ... read more |
| Category: News: News Archive 2013: |
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