Computational horsepower is always a concern for ASIC and SOC designers. I/O bandwidth is yet another. Configurable processor cores allow ASIC and SOC designers to add internal registers and function units that boost computational throughput, often by a factor of 10 to 100. However, increased computational performance places even more demand on the processor's I/O speed, to bring operands into the core and to ship results out. Conventional bus-centric design for on-chip I/O simply cannot handle the resulting increased traffic. Direct port I/O and FIFO queue interfaces can quickly ease the traffic load on overused buses, which greatly simplifies the design of complex chips.