November 24, 2004 -- Deep submicron technology enabled the design of the industry's first very large chips. The magnitude of the design effort involved in creating these chips led to the adoption of reuse methodologies and system-on-chip (SoC) design, in which various intellectual property (IP) components were created and reused to produce even larger, more complex chips. This led to the emergence of design flows and methods for handling IP protection and hierarchy, and ultimately SoC test.
SoCs can incorporate IP from one or more companies, and the benefit of testing the SoC hierarchically — offering the capability to isolate each section of a design for debug — is proving highly advantageous. By isolating the IP test, each test issue also becomes isolated to a specific block of the design.
By Teresa McLaurin and Rohit Kapur. (McLaurin is a consulting member of the technical staff at the ARM Design Center in Austin, TX and Kapur is Synopsys Scientist and guides the development of Synopsys DFT solutions based on Core Test Language (CTL) and other open standards.)
This brief introduction has been excerpted from the original copyrighted article.