Current traditional approaches to PCB design and manufacture meet up with numerous signal integrity problems at high data rates. Manufacturing artifacts such as inconsistencies in dielectric properties, inconsistencies in trace width, variation in circuit spacing, uneven copper thickness and/or adhesion treatments can impact signal performance. In addition, the standard electrical concerns of resistance, dielectric loss, conductor loss, stray capacitance elements, signal skew and inductance/cross talk and potential reflections due to electronic stubs from circuit features such as vias, also appear at high data rates. The net of this complex problem set is that they make it extremely difficult to predict and design for maximum performance.
While innovations in materials and manufacturing processes have yielded some improvements, the problems counted above are far from resolved. It is clear that a new and better way of addressing these problems is required. One simple approach is to simply avoid the traditional design approach path in favor of new design methods that partition the problem space into more manageable pieces.
This article describes a new approach which segregates the high speed signals from all lower speed signals and power and ground connections. In practice, high speed signal sources are interconnected with controlled impedance links that are fabricated separately from the PCB and later interconnected directly between IC packages where required. Thus, instead of trying to precisely control a complex printed circuit design into a monolithic interconnect, the signals are instead segregated and critical signals are shepherded to a more easily controlled interconnection paths that lead directly from chip-to-chip or chip to other suitable electronic device.
Circuit manufacturing and assembly technology has gone through several definable eras since the invention of the printed circuit board. A brief review of those eras helps in highlighting the incremental changes that have occurred over time.
- Early PCBs were simple, single metal layer structures designed primarily to replace discrete wire interconnections between simple components. Vacuum tubes were being replaced by early discrete transistors.
- The introduction of integrated circuits resulted in increased interconnect complexity requiring a second metal layer for circuits, power and ground distribution and plated through holes for side to side connections.
- Multilayer boards with internal power and ground internal layers, interconnected by plated through holes were developed in response to further advances in IC technology and the desire for increased functionality. This technology has remained fundamentally unchanged for nearly 20 years except for some innovative changes, such as the buried via, which helped to further increase board density and functionality and ease assembly.
- HDI (high density interconnection) technology, marked primarily by the presence of micro vias produced either by photolithographic or laser technologies, debuted in the 1990's as the successor to the much more expensive multichip module. HDI technology continues to serve the needs of high pin count packages such as BGAs, supplemented by new board construction technologies designed to provide increased interconnection density to support routing by embedding passives and providing distributed capacitance layers.
- The rebirth of the MCM as a "System in a Package" (SiP) technology is a recent area of industry interest and attention. Like previous innovations, SiP technology focuses on increasing density to yield greater functionality per unit space and greater localized performance. From a density perspective, solutions to date have been most impressive; leading edge SiP devices integrate up to eight or more chips.
While SiP solutions have focused on increasing functionality, reducing volume and lowering cost (as has happened in cellular phones), higher performance remains a never-ending priority in electronics. , Moreover, while SiP assemblies have met the challenge of higher interconnection density, at present they do not, in most cases, meet the high-speed signal integrity requirements interconnecting to circuit boards and improved approaches for designing and manufacturing low-cost interconnections for both current and future high performance electronic systems are needed. Thus there remains a gap in the needs of the industry that is likely to remain unfilled unless new approaches to circuit design and assembly are implemented.
Figure 1. The evolution of the printed circuit has been paced by the demands of IC technology. Complexity has increased significantly over the years but there are limits to what incremental technologies can offer in terms of cost and performance.
IC Package - PCB Co-design, an Alternative Approach
Chip-to-chip interconnection is the fundamental objective of electronics system board level design. However, the growing need for higher switching speeds has severely complicated this basic task, challenging the industry's ability to obtain ever-higher performance at ever-lower cost. Moreover, the increased power density associated with high-speed signals and the resulting thermal management problems exacerbates the problem. Although system-in-package developers are developing some very clever solutions for getting the heat out of these densely packaged silicon structures, SiPs bring appreciable risk.
The tension between performance demand, product size, product cost, and ultimate system reliability makes for hard design choices. If the devices are relatively inexpensive and manufactured using mature and predictable semiconductor technologies with known infant mortality, then SiP technology can be very attractive. However, when the IC die are cutting edge and expensive, the system designer is advisedly cautious about quickly embracing SiP solutions.
Although hand-held electronics, with their demand for ever-increasing functionality in ever-decreasing space, continue to drive interconnection technology, the performance demands of hand-held electronics are not as great as the demands for physically larger systems which are not so space constrained. These larger high-performance systems are thus open to other solutions that can provide the needed benefits in a cost effective manner.
The convergence of clashing objectives has created significant challenges and standard materials and design processes no longer meet the performance needs for high-speed interconnections. In fact, interconnection technology has now risen to the top level in terms of concerns from the system engineer's perspective. Fortunately, these challenges also offer the opportunity to rethink long-held approaches to circuit assembly design and how and where chips are interconnected.
Silicon technology has continued to double performance every 18-24 months since the 1970s, as per Moore's Law, however, copper interconnection technology performance remained virtually unchanged until the early 1990s when processor clock speeds exceeded PCB performance capabilities and processor designers were forced to use one clock for internal data transfer and a slower one for PCB transfers.
lthough PCB performance has improved in the last decade, today's PCB bus speed is pegged at 800MHz when using standard materials and design practices due to signal path problems such as those shown in Figure 2. Exotic materials provide some performance relief, but this relief is only temporary and the materials increase PCB costs. A better and long-term solution is to reconsider the design, manufacture and assembly of PCBs and route the highest speed inter-chip signals over a more direct path preferably through a controlled impedance channel. The question is how this can best be done. The answer is quite elegant: establish signal paths in all three dimensions of space.
Figure 2. Standard PCB materials and processing methods have a significant number of potential impediments relative to high speed signal processing. Many of the items enumerated have little impact for lower speed signals, however at higher speeds their impact can be major.
While traditional PCB design routes signals on, in and through the PCB, an improved approach to design routes signals both through and above the substrate with critical chip-to-chip signals flowing through controlled impedance interconnects mounted to the upper surface of the packages. This "elevated highway bypass" concept eliminates the traditional paths thought the PCB for high-speed signals and thus avoids all of the on-board circuit elements and features which destroy signal integrity and deliver poor high frequency performance. These elements, noted earlier, include:
- The metal conductor path including its height, width and length and its proximity to other circuit paths.
- The interconnection vias that the signal encountered over the course of the circuit path.
- Interconnection elements such as connectors and solder joints, etc., which are capable of creating signal discontinuities and disturbances that reduce performance capability.
- Signal skew which contributes significant routing challenges for designers trying to exactly match signal path lengths.
- Degraded signal rise time caused by dielectric loss.
- Conductor loss
- Other design features that can create impedance discontinuities.
While these parasitic-inducing design artifacts have been of little consequence in lower speed circuit applications (typically below 100 MHz), they are critical as signal speeds for digital systems enter the multiple gigahertz range. Improvements in materials and manufacturing processes have yielded some performance gains, but it remains clear that improved methods to address the underlying high frequency impediments are needed.
Figure 3. The OTT packaging approach significantly improves performance and simplifies the construction of both package and PCB, while bypassing the parasitic effects associated with most traditional design layouts.
The new approach picks up and delivers high speed signals "off the top" (OTT). The packaging design approach partitions the high and low speed design elements and routes them on different planes. Low speed power and ground signals are routed down through the package and into the PCB substrate while the high speed signals are routed directly off the top of one package to the top or tops of one or more other packages. The result is a very high performance interconnection path that does not require pre or post signal conditioning. Figure 3 provides a cross sectional comparison of the old and new approaches and Figure 4 provides a comparison of the simulation based eye diagrams for the two different methods over a common distance of 3 inches at 25Gbps.
Figure 4. The eye diagram comparison based on 3D field solver simulation data show an exceptional improvement is possible using the OTT technology (right) compared to the standard design approach (left) Data by TeraSpeed Consulting, Inc.
Because the upper surface of a typical chip pack is largely wasted space (except in case where devices are designed for stacking to improve density), this space can be used for selective interconnection between those circuit devices. This has significant benefits for high speed signals. By analogy, while old methods route signals on the equivalent of city streets and subways, (and high rise buildings in the case of stacked packages), the new proprietary approach allows for signals to be routed on the equivalent of controlled impedance, high-speed elevated superhighways that eliminate the circuitous and undulating circuit routes required by traditional approaches. A controlled impedance flexible circuit is most obvious electronic interconnection medium for OTT interconnects; many other interconnection structure embodiments could be used.
Figure 5. The use of OTT packaging concepts provides significant reductions in signal skew and assuages many of the other challenges of high-speed circuit design by segregating high and low speed signals thereby interconnecting simpler, more manufacturable IC packages and substrates.
Despite its compelling advantages, OTT technology will likely take some time to become mainstream because there are no conventions or standards for such packages (even though IC packaging foundries generally see no significant challenge to manufacturing them). Still, those who wish to use OTT today to connect two or more IC chips to communicate at native silicon speed can do so. The patent pending solution is relatively simple: an existing package can be easily adapted to the high speed task by simply attaching a rigid or flexible over lay extension to the surface of the existing package and ignoring the old signal paths and instead making direct connection from the chip to the high speed bypass. This is illustrated in the Figure 6. This technique also allows for the addition of separate driver chips to boost performance for longer distance transmission. Such devices could take the form of pre-tested IC packages joined and interconnected within another package .
Figure 6. The OTT packaging benefits are realized using existing packages and mounting and interconnecting a controlled impedance circuit to the top of a standard IC package. High-speed signals are bypassed on the existing package interconnections in favor of better controlled circuits on the cable. In cases where higher performance or longer distance is required, separate driver chip can be interposed.
Applications for Off the Top Packaging Technology
OTT concepts can be applied to a variety of applications. Figure 7 shows generic solutions for three application areas.
- Build memory subsystems by connecting memory chips and memory controllers to CPUs with OTT clean channels. One such memory solution allows standard DDR-II memory to be operated at a rate equivalent to 12.8 Gbps and with silicon design modifications the rate could be 2 to 4 times faster .
- Directly connect multiple chips such as FPGAs in a structure fashion . This solution allows product designers to create an unlimited "sea of gates" with little loss of time and without the need for expensive mask sets.
- Chip-to-connector solutions can be used for applications ranging from backplanes to test equipment. Chip-to-connector is an area of current development activity.
Figure 7. OTT packaging technology opens the door to a range of new interconnection opportunities including new memory architectures, ganging of FPGAs to create an unlimited "sea of gates" and higher performance chip-to-connector solutions for line card applications.
Direct interconnection between chip and connector provides a short path and relatively inexpensive solution to current challenges ranging from electrical test to telecommunications. While signal integrity engineers are quick to pick up on the benefits of the approach, a telecommunications demonstration is currently in development to prove the concept. A simple chip-to-connector solution was chosen for demonstration because it was determined that it could increase the overall performance of current generation switches, routers and memory storage farms by as much as 20% without the need for a "forklift upgrade" to a new system. Relatively simple modifications to daughter card designs would allow direct interconnection between the controller chip and the connector and obviate the need for more exotic and more expensive substrates while reducing system power needs.
Figure 8. A close up view of the elements of the test vehicle construction. Simple modifications to existing interconnection elements provide a cost effective path to creating high performance interconnections. (Note: The controlled impedance flex cable was being fabricated at the time of writing.)
While the concepts presented may be attractive for a range of applications, there are still a number of puzzle pieces, which must be put in place before broad scale adoption is achieved. With respect to IC packaging design, there is a need to establish appropriate methodologies and protocols in different areas. For example, there are no I/O planning and sequencing tools which address the creation of high speed interconnections between two distinct packages separately from those connections which are to be made through the PCB. That is, with the OTT approach all of the I/O are not considered for interconnection at the same time. This will require a new methodology: for coordination of what are effectively two different designs high-speed fixed interconnections so they can be considered once the packages are mounted on the PCB.
The PCB design and manufacture may well be less complex, because PCBs will not have to support high-performance circuit paths. However, PCB assembly will face some new challenges. For example, depending on the approach chosen IC package, alignment may need to be tightened so that the flex circuit or other interconnection schemes can connect reliably to one or more other packages once they are mounted on the PCB. There will also be a need to represent the top surface interconnections in three-dimensional space and current PCB tools are two-dimensional. Some of these 3D IC packaging issues are already being addressed in stacked wire bonded structures.
Electrical testing of IC packages and assembled systems can be simplified by OTT packaging. Having direct access to high speed signals makes full characterization of IC packages much less of a challenge and is an attractive alternative for future high performance package validation.
The move to high speed interconnections requires changes in the approach to design manufacture and assembly of electronics systems and thus a fundamental rethinking of the electronic industry's standard approach to overall interconnection architecture. The partitioning of PCB circuit layout, segregating high speed circuits from low speed and power and ground circuits, can eliminate the roadblocks to high speed chip-to-chip signal transmission and can be implemented by building dedicated high-speed interconnections that take advantage of the normally unused space on IC packages. This method facilitates the creation of shorter, cleaner signal paths that offer higher performance at lower power. Removing high-speed channels from PCBs means lower layer count packages and substrates and, ultimately, lower cost systems. These alternative approaches to design significantly improve the performance of electronic products with minimal disruption to the manufacturing infrastructure.
By Joseph Fjelstad, Gary Yasumura, Kevin Grundy, and Colin Mick. (Fjelstad, Yasumura, and Grundy are with SiliconPipe, Inc. and Mick is with the Mick Group.)
In addition to the efforts of their colleagues at SiliconPipe, the authors would like to recognize the following individuals and their companies and for their invaluable contributions and assistance in the prototype manufacture, assembly, testing and data analysis in the development of OTT technology:
Eric Bogatin, Bogatin Enterprises
Richard Brunsell, NxGen Electronics
Nader Gamini, Aeluros
Don Hayashigawa, NxGenEletronics
HT Ho, Possehl Electronics
Bernard Ambrosino, Possehl Electronics
HS Lam, Possehl Electronics
KM Lam, Possehl Electronics,
Brian Iwata, Heaton Co./ERNI
Robert Jung, AltaFlex
John Myrick, DuPont
Scott McMorrow, TeraSpeed, Consulting Group, Inc.
Go to the SiliconPipe, Inc. website to learn more.