January 24, 2005 -- As the number of production designs on nanometer geometries has increased, signal integrity (SI) has progressed from being a concern for a few leading-edge designers to being a pervasive nightmare for all designers.
Although several methodologies have evolved to address these SI challenges, the confluence of unintended electrical effects and burgeoning design complexity at sub-130 nanometer geometries is leading to an exponential number of reported SI violations. As a result, designs are suffering from prolonged design schedules and, often, missed market windows.
A key factor in the lengthening of the sub-130 nanometer design cycle is not only the increase in noise sensitivity, but also the excessive pessimism that exists in some SI closure methodologies and, in particular, SI analysis engines. While a reasonable margin is desirable to build the necessary guard bands to help designers tape out with confidence, excessive pessimism greatly increases design cycle time and leads to over-design.
Over-design often results in increased congestion, which hampers yield, and increased power, including leakage — a major concern for designs at 90nm and below.
Much of this excess pessimism comes from the underlying models used to estimate SI and some of the tradeoffs used to simplify the analysis process. Often, however, shortcuts in analysis lead to more design iterations due to over-fixing and over-constraining the design implementation. Hence, when selecting an SI closure or analysis solution, particular attention should be paid to ensuring that there is sufficient filtering of false violations.
By Rahul Deokar. (Deokar is senior product marketing manager for timing and signal integrity at Cadence Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the eeDesign (EE Times EDA News) website.
Read more about
Cadence Design Systems, Inc.