July 1, 2004 -- It is now possible to implement complete radar processing algorithms on a single multi-million gate FPGA. Most of these systems involve FFT processing along with other DSP algorithms. Clearly, FPGAs are coming into their own as devices for complex designs.

Dillon Engineering provides FPGA design services focused on creating DSP and high-bandwidth designs for real-time digital signal and image processing. Our multi-million gate designs include proprietary cores and complex DSP algorithms that comprise EDIF, Verilog and VHDL source, as well as various IP cores. Dillon has implemented several radar processing systems on single FPGAs in the last year, and our success in large part was based on an ability to reuse IP and the reliability of the tools available for its design flow.

Oftentimes, our success with these highly complex designs was hard won as we wrestled with severe timing closure problems in the projects caused by interconnect delays. We now know that high speed, multi-million gate designs that can be implemented in FPGAs, but those designs can have significant timing closure problems which can put project schedules at risk. New classes of FPGA design tools and methodologies are clearly required to address these challenges. We believe we’ve found those tools.

By Tom Dillon. (Dillon is president of Dillon Engineering, Inc.)