April 4, 2005 -- Bringing a new technology node (like the 90 nanometer node) online requires the creation of special parametric test chips. Until now, these test chips have been created by hand and the ensuing electrical and process-related data has been managed using spreadsheets. Now, Stone Pillar Technologies is providing tools to automate this process.

The Test Chips are coming; The Test Chips are coming…

I'm constantly amazed by the amount of stuff I don't know. To a large extent, of course, I don't actually know what I don't know … it's only when I run into something new that I think to myself "Well, tickle my toes with a mallet, I didn't know that!"

Hmmm, perhaps this isn't helping as much as I thought it would. Mayhap we should turn to US Secretary of Defense Donald Rumsfeld who, when trying to clear up a point of confusion, informed everyone that "… as we know, there are known knowns; there are things we know we know. We also know there are known unknowns; that is to say we know there are some things we do not know. But there are also unknown unknowns - the ones we don't know we don't know."

You have to hand it to the man - he's captured things in a nutshell. To provide a case in point, just a few short weeks ago as I pen these words, I'd never heard of the term "Test Chip" per se, at least, not in the context used by chip foundries. Who knew that these little rascals were poised to have an impact on the developers and users of EDA tools? Ah, how I remember those happy, far-off times so replete with fun and frivolity. By comparison, I now know more than I ever wanted to about test chips (and the scary thing is I've only scratched the surface of a deep, dark topic).

The way it was (and still is in the majority of cases)

I hadn't really thought about this before, but when a new technology node (like the 90 nanometer node) is poised to come online, there are all sorts of tests that have to be made. These tests go way beyond simply creating a few sample wafers to ensure that everything is "spit-spot" (as Mary Poppins would have it). The point is that - I was aghast to learn - no one can really predict with any level of accuracy how a new process is going to behave; instead they have to build things, measure the results, and only then say "this is how it behaves."

In order to do this, the foundry builds a wafer covered with (typically) identical copies of a parametric test chip. This test chip is itself covered with copies of a single transistor, but each transistor copy has a slight variation from its predecessor. For example, consider just a few common attributes such as the transistor's width, depth, and poly-to-contact spacing. Each of these attributes can be varied across a range of values, so the test chip will contain myriad copies of the same basic transistor encompassing every combination and permutation of the different attributes.

"And how are these transistors captured," you cry. Well, believe it or not, the prevalent technique is for some poor soul to spend hour-after-hour, day-after-day, week-after-week pushing polygons by hand. Not surprisingly, in addition to being incredibly boring, this technique is prone to error to say the least. Let's suppose that this unfortunate has a "bad polygon day" and some transistor we'll call 'X' ends up with a slightly erroneous width, for example, tracking this down later in the process can be a pain in the … you get my drift.

But wait, there's more. A modern wafer fabrication flow comprises literally thousands of different events, and variations in each of these events can affect the characteristics of the ensuing transistors. In the case of a heat cycle, for example, we might vary the amount of dopant gas in the oven, the maximum temperature, the ramp-up time to that temperature, the sustain time at that temperature, and the ramp-down time back to ambient temperature. Similarly, in the case of an ion implantation step, we might vary implantation energies, angles, and dopant mixes and levels.

What the foundry is looking for is the "sweet spot" in this multi-dimensional solution space - that is, the ideal combination of transistor structure sizes and process steps that will result in the "perfect transistor" for this process (I'm simplifying things of course, but trust me, it's better not to know the grim and grimy truth).

Finally, the foundry constructs lots of test chip wafers under different combinations and permutations of process steps. Then a piece of automatic test equipment is used to probe each and every transistor measuring things like switching speeds, threshold voltages, leakage currents, and so forth.

The result is a morass of data. And how is all of this data managed these days? Well, believe it or not, the state-of-the-art for most foundries comprises a lot of big, hairy spreadsheets. Now I'd be the first to agree that spreadsheets are wonderful tools for certain tasks, but wading through mountains of the things trying to correlate the results of varying different process steps and varying the sizes of different transistor structures is not one of them.

The way it's going to be …

Creating test chips and managing the parametric test chip data associated with the different process variations is obviously a task that calls out for automation. The reason it's taken this long for such automation to make an appearance is that things are way more complex than I've presented them here.

Having said this, one company - Stone Pillar Technologies (www.stonepillar.com) - is paving the way in this arena. Using the various tools encompassed by their Silicon Insight Application Framework, engineers can now quickly and easily:

Generate a new test chip Capture the steps in the wafer fabrication flow Generate a database in which to store the results Control the automatic test equipment that measures the electrical characteristics associated with each transistor Store this parametric data in the database Analyze the data to correlate structure sizes and process step variations so as to find optimal combinations

As one simple example (the first point in the above list), the engineers can provide a range of values (minimum, maximum, and step) for all of the parameterizable elements associated with a transistor, such as the poly-to-contact spacing and the widths and depths of various structures. Then, by simply clicking the "Go" button, the system automatically generates the GDSII files required to construct the chip's photo-masks. Furthermore, the system also outputs details as to the locations of the transistors and their probe points for use by the downstream automatic test equipment that will determine the electrical characteristics of each device.

Cool Beans

When test chips are created by hand, it can take two-to-three months to build the first wafer; thereafter, one can generate one or two new test chip wafers every month or so. The point is that - when you have a pack of wild design engineers straining at the leash and slavering to start working with a new technology node - each and every month is a painful delay they would be happy to live without.

Now, when using Stone Pillar's technology, the time to generate the first wafer can be reduced to just a few days; and once this initial offering is out of the door, it's possible to generate hundreds of variant test chip wafers in a matter of hours.

The end result is that any foundry using an automated process has a huge advantage over its non-automated competitors and - more importantly to folks like me - end user design engineers can get their hands on "the goodies" much sooner.

Once again, everything I've said here has been a gross simplification. The reason it's taken so long for automation to arrive in this space is that these things are outrageously, horrendously, complicated. The guys and gals at Stone Pillar are techno-dweebs of the highest order (I mean this as a complement), and they've finally cracked the problem and are providing cutting-edge foundries with absolutely state-of-the-art technology. So it's an official "Max's Cool Beans" award to Stone Pillar (and all who sail in her) from me. Until next time, have a good one!