February 24, 2003 -- "New chip development cycles have decreased to a year, and the time to create a derivative has shrunk to six months. How can chip verification, which takes up 50 to 70 percent of today's development cycle, keep pace?
"One way to reduce development time is to reuse the verification environments created in other domains, such as the system domain. These environments generally are created in C++ and traditionally have been inaccessible to digital-verification engineers. With the acceptance of SystemC and the SystemC Verification Library, it is feasible to reuse this environment to save time."
By Leonard Drucker. (Drucker is senior Core Competency technical manager for the Systems Verification group at Cadence Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
