May 1, 2005 -- Nanometer technologies contain newer types of defects that are delay sensitive and can no longer be detected with traditional stuck-at tests. High impedance shorts, resistive vias and bridges, in-line resistance, and crosstalk between signals are some of these newer types of defects that are commonly seen in today's nanometer designs. Since many of these newer defects cause faulty timing behavior rather than faulty logic behavior, they can be effectively caught only by applying the tests at system speeds. This has led to the required use of delay-based fault models in Automated Test Pattern Generators (ATPG) to target these defect types. Transition faults and path-delay are two delay-based fault models that are widely used today while performing at-speed testing.

Studies have proven that the detection of defective parts by manufacturing delay tests test depends on the test timing of the launch and capture clocks [1]. Fewer defects are detected when tests are run at speeds slower than the operating speed of the device (under normal operating voltage). As demonstrated in [2], delay defects are affecting chip quality and scan based delay test is the most efficient and most effective chip manufacturing test to address the problem. In many applications, the launch and capture clocks need to be generated on-chip, via the use of test clock control logic is usually referred to as On Product Clock Generation for test (OPCG).

In many applications, delay tests that run at the clock domain speed are not sufficient. To detect small delay defects, the tests need to run at the tightest possible timing, and for many transition faults that means running faster than at-speed. The OPCG solution needs to support the generation of clock pulses with a duty cycle that is faster than the actual clock domain speed.

Generating launch and capture clocks for delay tests

In order to apply delay test, the launch and capture clocks must be delivered at functional circuit speed. There are two possible sources for these test clocks. One is the external Automatic Test Equipment (ATE) and the other is on-chip clock generation. Traditionally, ATEs have supplied the test clocks. In many cases, the ATE is still a viable source of clocks for at-speed testing. However, as the sophistication of the ATE and its test fixtures increase in order to meet at-speed clocking accuracy requirements, the cost significantly rises. Most common testers offer clock speeds under 200 MHz [4]. Many designs now operate at much higher frequencies. There is a practical limit to source the clocks from an ATE, either limited by cost or bandwidth. Once this limit is reached, the clock has to be sourced from on-chip clock circuitry.

More and more designs now include a phase-locked loop (PLL) or other on-chip clock generating circuitry. The system clocks for these devices are often provided by an embedded on-chip phase-locked loop (PLL) or delay locked loop (DLL).

PLLs are most often used to generate a high speed clock from a relatively low frequency reference clock. A typical PLL design can be programmed to increase or decrease the clock frequency by a predetermined factor. The PLL output frequency is precisely locked to the reference frequency. If the reference frequency changes the output frequency changes proportionally. Figure 1 conceptually shows how a slower test clock signal goes into a PLL and comes out as a faster (2X in this case) clock signal. In many PLL designs there are programmable settings to select the PLL's frequency multiplication factor.

Figure 1. Concept of PLL generating a faster clock signal.

Test clocks using On Product Clock Generation

In order to use the PLL for delay test, there are requirements for additional control circuitry that can on command generate the launch and capture clocks at the desired duty cycle. This control logic is usually referred to as On Product Clock Generation for test (OPCG).

A simple example of OPCG is when the delay test might use a trigger event to emit a sequence of synchronized pulses to the internal clock distribution and then stop, allowing the responses to be scanned out as shown in Figure 2. Before gating the oscillator signal, the trigger must be synchronized so as to prevent the possibility of turning the clock "on" or "off" in the middle of a pulse. This is the purpose of the three flip flops in Figure 2. Here, in the figure, the "outputOPCnet" is referring to the output on product clock circuit.

Figure 2. External trigger OPCG example.

The resulting waveforms of the PLL output signal and the signals on locations A, B, C and the output of the synchronized logic (outputOPCnet) are shown in Figure 3.

Figure 3. Resulting waveforms for external trigger OPCG example.

Another example of OPCG is shown in Figure 4 . In this case an external chip signal controls the on-off function of the clock. In response to an upward transition on the "scan" signal, a predetermined number of clock pulses are to be emitted. In this implementation, a binary counter controls the PLL output gate. Also, a single shot is used to reset and start the counter, which automatically stops when the count reaches "0".

Figure 4. Single shot OPCG example.

A faster clock signal can be generated from the available slow tester clock signal by means other than a PLL. In one technique, the slower clock signal from the tester can go through some clock choppers and gating logic and a faster release-capture clock pair can be generated inside the chip to support delay testing. A sample of a combinational logic of clock choppers and some gating logic is shown in Figure 5.

Figure 5. Clock chopper OPCG concept.

Figure 6 shows the three clock chopper output signals O1, O2 and O3 are ORed together to produce a faster O4 signal. This new signal is 3X faster than the Input Clock and can be used as both release and capture signal for at-speed delay testing. The waveform table for the original input signal and the O1, O2, O3 and O4 signals are shown in Figure 6 below.

Figure 6. Resulting waveforms for clock chopper OPCG concept.

Generating faster than "at-speed" tests

The OPCG methodology supports the requirements of Encounter True-Time Delay Tests to test at the tightest possible timing to detect small delay defects. True-Time delay test can run faster than at-speed to identify subtle defects that exist in nanometer designs. In addition, True- Time delay test can detect delay defects on non-critical paths that even at-speed tests will miss. True-Time delay test includes an on-board timing engine and uses post-layout timing data from the SDF file to calculate the path delay of all paths in the design, including distribution trees of test clocks and controls. Using clock sequences available from the OPCG, True-Time will generate a test for the smallest cycle time, followed by the next larger cycle time, and so on. At any particular cycle time, flip-flops observing paths longer than this specified cycle time will be masked out, eliminating false miscompares on the tester. This methodology has been demonstrated to generate the highest quality transition test.

Specifying On Product Clock Generation to the ATPG

To create and deliver highly accurate delay test patterns, the ATPG tool needs to understand the operation of the OPCG logic. In Figures 2, 4 and 5, the output net of the PLL clock circuitry has been identified as "OutputOPCnet". This net can be treated as a pseudo-primary input by the ATPG product. A pseudo-primary input is a conceptual modeling device that does not represent anything physical in the circuit, but is used to provide contact in a logical sense with internal nets. Several of these types of faster clock signal nets may share the same pseudo-primary input. The ATPG behaves as if each "outputOPCnet" was disconnected from the PLL/chopper circuitry and connected instead to its associated pseudo primary input. In addition, by defining custom test sequences, the user can specify the functionality and relationships between this pseudo primary input and the Input Clock that goes to the PLL or clock chopper circuitry.

To recognize and treat the output net of the on product clock circuitry as a pseudo-primary input the testmode has to contain with the pseudo primary input definition. The user can either explicitly identify nodes of the design netlist, or specific cells in the library can be attributed to identify the nets internal to the design to be treated as pseudo-primary inputs. By using the custom test sequences, the ATPG generates test patterns by treating the specified pseudo-primary input clock signal as it would a real (primary input) clock with pre-defined sequences.

Figure 7 provides an example of this process with Cadence's Encounter True-Time Delay Test. The specification defines the "outputOPCnet" as a pseudo primary input during the testmode definition and the custom test sequence. In this example, the relationship between the original clock signal and the specified cutpoints specified in Figure 5 has been defined using the custom test sequence.

Figure 7. Test sequence template for clock chopper OPCG concept.

The sequence template in Figure 7 can also be easily described using the following flow:

The CUTPOINTS statement shown in the Figure 7 specifies that ppiC is a pseudo primary input that controls the net outputOPCnet. The logic states to be imposed on ppiC will be seen non-inverted (indicated by the plus sign) on net outputOPCnet. The ASSIGN statement declares that ppiC is a clock signal (ES) with a quiescent state of 0 (-). In this example, the clock generation logic was not programmable and would always produce the same sequence of pulses on the pseudo-primary input. When the clock generation logic includes some programmability, the custom test sequence can have a setup sequence associated with it. The setup sequence defines how to program the clock generation controls to ensure the clocking shown in the test sequence will be produced. The setup sequence needs to be applied only when switching to a new clocking sequence.

Once the ATPG patterns are generated using the user specified "Custom Test Sequence", they can be applied to the chip using either a slow tester clock (no PLL), or a slow trigger signal (with PLL). When using a PLL, it is best to start the input oscillator and lock the PLL onto it while initializing the test mode, ensuring that the PLL will be locked while the test mode is active. The clock control function utilizes the high-speed clock output from the PLL (or the clock chopper) circuitry and allows a fixed-length sequence of pulses to be produced to the internal logic. This is a convenient and highly effective way for applying delay patterns to devices that contain their own clock generation logic.

Using the method described above, the majority of commonly used OPCG methods can be handled by the ATPG tool. Using cutpoints and pseudo-primary inputs, ATPG ignores the clock generation logic, which may be modeled as a black box for ATPG. As a separate step, verification of the custom test sequence will, however, require a simulation model of the clock generation logic and will verify its operation.

Conclusion

Nanometer technologies and increasing clock speeds are resulting in an increasing occurrence of delay defects. Delay defects negatively impact product quality and cannot be detected with tradition stuck-at scan tests. Scan based transition fault testing is required component of the manufacturing test process. As frequencies increase, delay test will require On Product Clock Generation (OPCG) for generating the test clocks. This article has described a methodology that supports the use of OPCG in delay test generation.

By Anis Uzzaman

and

Carl Barnhart

Uzzaman is a Member of Consulting Staff in the Encounter Test group of Cadence. Prior to Cadence, Anis worked on EDA solutions for IBM Microelectronics. Anis has a B. Eng degree in Electrical Engineering from Tokyo Institute of Technology, Japan and an MS degree from Oklahoma State University.

Barnhart is a servo designer by training (BS, U.S. Naval Academy and MSEE, Stanford University), a logic designer by practice (IBM, over 28 years), and a design-for-test expert by accident (also IBM....) Carl is currently education lead and architect for the Encounter Test products at Cadence Design Systems, San Jose, Ca.

The authors would like to acknowledge the input of Brion Keller, Tom Snethen, Thomas Valind, Vivek Chickermane and Krishna Chakravadhanula on this topic.

References:

[1] Delay Defect Characteristics and Testing Strategies, K.S.Kim, S.Mitra and P.G.Ryan, Design & Test of Computers, Vol.20, No. 5, pp. 8-16

[2] Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits, J. Gatej et al., Proc. Int'l Test Conf (ITC02), IEEE Press, 2002, pp.1111-1119

[3] Using Static Timing Analysis to Drive Delay Pattern Generation, Alfred L. Crouch, Inovys Corp., 2004 Southwest Test Conference, Austin,Texas.

[4] Exploring the Basics of AC Scan, Alfred L. Crouch, Evaluation Engineering, July 2004