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Mentor Graphics Extends Catapult C Synthesis Product  
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May 2, 2005 -- Mentor Graphics Corp. has announced extensions to its Catapult C Synthesis algorithmic synthesis tool to automatically create SystemC transaction-level models and wrappers, allowing designers to rapidly explore architectural tradeoffs and simulate their designs 20X to 100X faster than traditional register transfer level (RTL) using verification environments that support SystemC, such as Mentor's ModelSim.

"The combination of algorithmic synthesis from pure ANSI C++ with an integrated SystemC verification environment provides a powerful solution for ESL design," said Simon Bloch, general manager of the Mentor Graphics Design Creation and Synthesis Division. "Designers now have a methodology for easily implementing a 'golden source' from the algorithmic level of abstraction down to technology-specific RTL. With the ability to generate SystemC models, designers can now rapidly explore architectural tradeoffs and verify their design, while re-using existing C++ and SystemC testbenches throughout the flow."

Venkat Rangan, senior staff engineer for Qualcomm, commented on the Catapult C Synthesis verification extension, "The new enhancements to Catapult C promise to automate the time-consuming process of SystemC model creation. Automatic SystemC model generation has great potential to accelerate block- and system-level verification, which would enable designers to produce better hardware much faster than before."

Traditionally, designers had to manually re-write their C algorithms into SystemC, a slow and painstaking process of incremental refinement, adding the structure, parallelism, and interfaces necessary for SystemC. Instead of this manual progressive refinement, the Catapult C Synthesis tool now automatically adds these hardware details to the algorithmic C++ model to generate a cycle- and bit-accurate behavioral SystemC model.

Hardware designers can then employ Mentor's scalable verification platform to rapidly verify generated models. The interface of the SystemC model has the same behavior as the RTL generated by Catapult C Synthesis, but is optimized to simulate 20-100X faster. Designers can, therefore, more rapidly explore and verify architectural tradeoffs and achieve faster verification of their optimized designs.

The Catapult C Synthesis tool lets designers use algorithmic C++ models as a "golden source." The tool employs interface synthesis and sequential-to-structural transformations to automatically generate SystemC or RTL hardware descriptions without changing the original sequential C++ source. Currently, Catapult C Synthesis uses C++ to produce behavioral SystemC models that simulate 20-100X faster than RTL, with future releases intended to generate more abstract transaction-level SystemC models that simulate more than 1000x faster than RTL.

The tool's interface synthesis technology also helps generate transactors that synchronize timed RTL with a sequential or transactional test environment. This connection allows designers to use a single sequential C++ or SystemC-based testing environment for the entire design flow. Catapult C Synthesis can also generate a testbench that automatically compares the C++ input to the RTL output, providing debug information for specific synchronization points in the case of a simulation mismatch. These capabilities allow designers to use or re-use sequential C++ descriptions and testbenches to generate technology-specific hardware without actually modifying the algorithmic model, delivering on the promise of a C++ golden source.

Pricing and Availability

The price of the Catapult C Synthesis tool currently ranges from $89,000 to $275,000. The tool is available immediately on both term and perpetual licenses.

Go to the Mentor Graphics Corp. website for details.

Read more about
Mentor Graphics Corp.

Keywords: Mentor Graphics, Catapult C Synthesis, electronic system level design, ESL, C/C++, SystemC, EDA tools,
199/13121 5/2/2005 6853 942
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