June 20, 2005 -- Sequential equivalence checking gives designers
another functional verification option. By proving equivalence between designs
with sequential differences, all previous functional verification investment is
leveraged across future RTL implementations.
Sequential equivalence checking ensures functional correctness of
micro-architectural transformations, giving designers the confidence to make RTL
changes late in the design process. This technology also offers quick detection
of side effects and ensures RTL optimizations remain consistent with the
original functional intent.
By Mitch Dale, Duncan MacKay, and Venkat Krishnaswami.
(Dale is Director of Product Marketing, Mackay is a Methodology Consultant, and
Krishnaswamy is Director of Engineering and cofounder of Calypto Design Systems,
Inc.)
This brief introduction has been excerpted from the original copyrighted article.
