July 11, 2005 -- These days, "design for manufacturing" (DFM) and "design for yield" (DFY) are frequently used terms in the EDA industry. It has been said that yield should be the "fourth design parameter" after area, timing and power. True, improving yield has in the past been left mostly to the fab and has had little direct impact on IC designers. It is well understood that this is no longer the case at the 90-nm and 65-nm nodes due to difficulties of lithography and manufacturing.
Designers and design tools must start optimizing designs for yield prior to taping out the chip. Despite the buzz, designers are left with few answers to some basic questions: How big of an issue is yield in my design? How to measure the yield? What can be done in my design to manage and improve yield?
Joe G. Xi. (Xi is the vice president of product marketing for digital IC products at Cadence Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
