July 22, 2005 -- Design for manufacturability (DFM) has become one of the most talked about areas in electronic design automation (EDA). The challenges associated with power, yield, leakage and mask patterning at 90nm process nodes and below have become the subject of a great deal of discussion, debate and venture capital funding in recent times. The DFM segment of EDA is regarded as one of the few high growth areas in an otherwise stagnant industry.
Startup companies seem to form on a daily basis, many focused on solving the DFM problem, with the promise of improving yield and overall quality for costly new fabrication facilities. Yet, in the face of all this discussion, investment and activity, there remains one simple fact: No one can clearly define the problem and explain how to solve it.
Simply put, new EDA product roadmaps are broken. The evolution of successful EDA tools and methods has taught us one important lesson: integrated solutions win. The early pioneers of our industry proved this when they integrated schematic capture tools with simulators and waveform displays. More recent innovations have linked synthesis with place & route. Great progress has been made on many fronts, but a significant barrier for integration looms on the horizon: the barrier between design and manufacturing.
Consider the world that is depicted in Figure 1. In this world there are two distinct disciplines dependent on each other for a chip's ultimate success, yet each group knows little about the other.
Figure 1. Design and manufacturing think differently and work differently, creating a real barrier for communication (The Tapeout Wall).
The design community thinks in terms of circuit and geometry information, but the manufacturing community thinks in terms of geometry and process information. The languages are fundamentally different. This barrier will have devastating effects as semiconductor processes shrink below 90nm. Why?
Because of the combined effects of complexity and predictability. An example will illustrate the point. When design complexity grew to the point that the delay contribution of routing became dominant, it was no longer acceptable to estimate delays based on wireload models and "fix the problem later." The predictability was poor with this approach. Instead, the routing function needed to be tightly integrated with the synthesis function so real results were available earlier in the process.
How do we fix it?
We now face this same type of problem at 90nm and below but with vastly more difficult integration challenges. Subtle process effects have ramifications on chip power, reliability and performance. Reticle enhancement techniques are required to improve circuit printing fidelity, but the layout designer has little to no knowledge of how those changes will affect the circuit.
Designers need to ensure critical circuit elements are treated differently to optimize their performance, but there are no methods or tools to accomplish this. Even if the designer could communicate the identity of critical nets, the manufacturing tools have no way of dealing with this information.
The world depicted in Figure 2 should be our goal. Implementing this vision requires new tools on both the design and manufacturing sides of the tapeout wall; - tools that can deal with information from the other side of the wall in a meaningful way. The vision also requires new information architectures that merge circuit, geometry and process information, so that all views of the design and its associated implementation can be considered at every step of the process.
Figure 2. Creating a common language and methodology eliminates barriers and allows meaningful communication.
If we define the problem in these terms, a true DFM solution must address two critical requirements:
- Improve the design engineer's ability to access accurate manufacturing information and use it in a meaningful way to improve the quality of the final product
- Improve the manufacturing engineer's ability to understand design intent, and act on that knowledge in a meaningful way to improve the quality of the final product
Applying this definition of DFM to the myriad new approaches and ideas will have a clarifying effect. Point tools that don't provide a roadmap for meaningful communication across the tapeout wall are not DFM tools. Information architectures and data communication schemes that provide no applications to process the information in meaningful ways are not DFM tools. Adherence to this definition of DFM will quickly identify the true leaders in this market.
By Mike Gianfagna, CEO, Aprio Technologies, Inc.
Go to the Aprio Technologies, Inc. website to learn more.