March 3, 2003 -- "The integration of test capabilities into the underlying structure of an ASIC eliminates the extra design-for-test (DFT) steps that complicate conventional front- and back-end design flows. Rather than distracting from the primary design goals, this DFT approach takes no extra time. In fact, overall design and production turnaround time decreases along with costs because robust DFT structures can be integrated with significantly less effort than with a standard ASIC. Additionally, the layout of the DFT structures does not interfere with the chip's other functions.
"The key to this type of ASIC is its use of embedded intellectual property (IP) combined with an array of logic elements that you can use as needed. The embedded IP can include DFT structures such as boundary scan, internal scan, built-in self-testing (BIST) and IP testing as well as circuitry to minimize clock skew and signal-integrity issues."
By Steven Kawamoto, Gaku Ogura, and Richard Lee. (Kawamoto is Sr. Marketing Manager, Custom LSI Solutions Unit, Ogura is Sr. Marketing Manager, Design Solutions Center, and Lee is Design Engineer, Design Solutions Center with NEC Electronics America, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Engineering Times (EE Times) website.
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