October 10, 2005 -- During the past five years, ASIC system-on-chip design has taken on a new dimension — namely, that of ASIC SSOC (supersystem-on-chip) design. SSOCs have multiple processor cores and buses, and more than 10 million logic gates. The added design content is made possible through reusable intellectual-property (IP) blocks. A simple SSOC may require 30 engineers, but the ASIC teams of today still consist of 10 or so engineers.
SSOCs have changed ASIC development teams to ASIC integrator teams. An ASIC integrator team's prime responsibility is the verification of the SSOC to test for functionality and manufacturability, and to interface with the fabless supplier in order to take the SSOC ASIC to production. Traditional ASIC development teams — working at the gate level — now mostly develop IP or validate IP from a supplier. This means that new ASIC/IP development teams need to have a flexible design environment, and must be able to add IP from different vendors and test it even before the IP is purchased.
By Mobashar Yazdani and Mike Stahl. (Yazdani is an ASIC program manager at Hewlett-Packard Co.'s Global Operations; Stahl is an alliance manager/design technology scientist at HP's Hardware Systems and Technology Division.)
This brief introduction has been excerpted from the original copyrighted article.