November 23, 2005 -- The adoption of FPGAs in more markets and systems every year reflects the successful efforts of leading FPGA vendors to push the envelope in process technology, performance/density, and price. Recently however, the move to 90nm has challenged FPGA vendors to do more than just extract maximum density, features, and clock cycles. This latest process node has introduced a new set of coincident issues regarding minimizing power consumption. This article will explore the various power considerations that can be addressed by the FPGA vendor and the end user.
In order to compete for sockets in many prime target applications, vendors must find ways to enable the designer to reduce FPGA power consumption in the entire system. Excessive power is expensive in many ways; it creates the need for special design and operational considerations – requiring everything from heat sinks to fans to sophisticated heat exchangers. Even the cost of larger power supplies as well as energy charges must be taken into consideration.
Managing power within the system budget is essential not only to reduce capital and operational expenditure, but often to maintain reliability as well. As their junction temperatures rise, transistors consume more power, thereby further increasing the temperature of the device. Left unchecked, this positive feedback loop can lead to thermal runaway.
By Anil Telikepalli. (Telikepalli is Senior Manager, Virtex Solutions, Xilinx, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Programmable Logic Designline website.
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