February 2, 2006 -- Design-optimization methodologies and flows that
use gates with two threshold voltages (VTH) can achieve excellent
results for both power and timing with a high degree of automation. This
dual-VTH approach has become crucial for VDSM (very-deep-submicron) chips, in
which reduced VTH not only improves performance, but also increases
static (leakage) power.
In fact, leakage power increases exponentially with the technology scaling
and reaches 50% of chip power at 65 nm. This dramatic increase in leakage power
is unacceptable for most designs, whether or not they run from battery power. As
a result, most designs can benefit from design-optimization flows that balance
the trade-offs between performance and leakage power.
There are three popular flows for optimizing performance and leakage power
based on design requirements. These flows target minimum leakage, best
performance, and optimum chip area and tool runtime for a design in power-on
mode. Because the design still consumes leakage power in standby mode, the flows
also include methods for minimizing standby leakage power.
By Kaijian Shi. (Shi is a principal consultant with
Synopsys Professional Services.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.
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