Native SystemC Assertions(NSCa), is a scalable System to RTL verification solution that provides native assertion mechanism in SystemC. In its first release, NSCa provides assertions constructs very much similar to those in SystemVerilog Assertions(SVA).
NSCa provides the capability of writing assertions primarily in two ways. One, by providing
the NSC syntax, a natural extension of the SystemC/C++ syntax to support the notations for
assertion. The code written using the NSC syntax is translated to SystemC/C++ code by the
NSC Translator. The second option is it uses assertion NSC macros that provide the same
functionality like C macro forms. With this option, the user can stay within the standard
C++ syntax and simply makes assertion macro calls.
Either using the NSC syntax or macro, the users can embed the assertion code into any
SystemC program without any restriction. The code can be a property monitor that checks
the design behavior throughout the entire simulation, or a single program code to check the
sequence at the given time slot of the program execution. The user can use the temporal
expression written directly as the condition expression of an if statement or a while
statement to construct the self-checking testbench code. This flexibility extends the
programmability of SystemC over the temporal event evaluation.