In nanometer designs (130 nm or below), interconnect plays a dominant role in silicon performance. With coupling
capacitance dominating total capacitance (for some nets, coupling accounts for more than 80 percent of total
capacitance), and with higher clock frequencies and lower supply voltages, nanometer designs suffer from an
increased sensitivity to signal integrity (SI) effects such as crosstalk-induced delay changes and functional failures
caused by crosstalk glitches. The resulting costly silicon respins and extended design cycles lead to delayed time to
market, under-performing chips, and lower yield.
In the pre-nanometer design era, SI effects typically were either analyzed and repaired manually after timing closure
or ignored altogether. This approach does not work at nanometer-level geometries because both the number of
potential violations and their likelihood of seriously impacting the design increase dramatically. Reduced feature
size, decrease in interconnect pitch, and lower power supply voltages all contribute to SI-induced functional failures
and timing problems. In addition, because wire resistance is increasing and power supply voltages are
decreasing, designs are far more vulnerable to power supply variations (IR drop). IR drop has a negative impact on
performance and increases sensitivity to crosstalk—which also impacts timing. This vicious cycle can play havoc with
design schedules and can be a major root cause of silicon failures.
Leaving SI problems for post-route analysis and repair often results in an unpredictable design schedule that can
easily spin out of control as the potential SI violations far exceed the work that can be managed effectively. To
mitigate the risk of a major schedule slip and to improve the chances of first silicon success, designers must address SI
issues concurrently with implementation.