Page loading . . .

  
 You are at: The item(s) you requested.Friday, September 03, 2010
Xilinx Delivers High-Speed Interoperable Interfaces for Latest Texas Instruments DSPs  
 Printer friendly
 E-Mail Item URL

March 1, 2006 -- Xilinx, Inc. has announced the immediate availability of two interfaces for Texas Instruments, Inc. (TI)  DSPs. The Xilinx Serial RapidIO interface for use with Virtex-4 and Virtex-II Pro FPGAs provides up to 10 Gbps serial links to TI's High Performance TMS320C6455 DSPs. This high-speed industry standard link lets DSP designers targeting TI DSPs use Xilinx FPGAs for DSP acceleration, bus bridging, logic consolidation or implementing new peripherals. The new VLYNQ interface provides a bridge to the CoreConnect bus on Xilinx low-cost Spartan-3 and Spartan-3E FPGAs, letting designers use FPGAs to expand the number of peripherals for their DaVinci-based TMS320DM644x Digital Media Processor, or any TI DSP with a VLYNQ interface.

"Collaboration with DSP ecosystem leaders such as TI is a cornerstone of our digital signal processing strategy and roadmap," said Omid Taheirna, General Manager and Vice President of the DSP division at Xilinx. "These new interfaces build on the co-processing platforms we delivered last year and pave the way for more synergistic solutions in the future"

The Serial RapidIO interface provides a very high speed connection between the FPGA and TI C6455 DSPs which enables high throughput for both data and clock. Xilinx RapidIO interface supports x1 and x4 lane Serial RapidIO links in both the Virtex-4 FX and Virtex-II Pro FPGA platforms. Both x1 and x4 lane configurations support operating link speeds of 1.25 Gbps, 2.5 Gbps, and 3.125 Gbps per lane. With the Xilinx Serial RapidIO interface designers can implement unique and flexible high performance architectures using TI DSPs in applications such as wireless and telecom infrastructures, digital video, and imaging.

VLYNQ is a serial low-pin count communications interface capable of operating up to 125MHz. The new Xilinx VLYNQ interface provides a bridge to the CoreConnect On-chip Peripheral Bus (OPB) available on Xilinx FPGAs. With the Xilinx VLYNQ interface, designers can use TI TMS320DM6443 and TMS320DM6446 Davinci-based processors to communicate to custom-built or standard microprocessor peripherals such as such as extra UARTs and SPIs implemented on Spartan-3 and Spartan-3E FPGAs, providing a flexible and differentiated system solution to better meet changing market needs. The new VLYNQ interface follows the successful delivery of the EMIF interface and video-co processing kit for the DM642EVM by Xilinx. While designers can still communicate between Xilinx FPGAs and TI DSPs via the EMIF interface, they now have the choice to interface to FPGAs using VLYNQ and use the EMIF interface exclusively for interfacing TI DSPs to external memory, thus delivering higher system performance.

Pricing and Availability

The Xilinx VLYNQ interface is available now and priced at $995. The Serial RapidIO Physical Layer and Logical (IO) and Transport Layer Interface LogiCOREs are available from Xilinx today. The list price is $15,000 for the Physical Layer LogiCORE  and $10,000 for the Logical (IO) and Transport Layer Interface LogiCORE.



Go to the Xilinx, Inc. website for details.
 Please click here to let us know if the above link is broken!

Read more about
Xilinx, Inc.
and
Texas Instruments, Inc. (TI)
on SOCcentral.com


Keywords: Xilinx, Texas Instruments (TI), Serial RapidIO, sRIO, DSP, digital signal processing, FPGAs, field programmable gate arrays, intellectual property, IP, cores,
552/18176 3/1/2006 1655 231
Designer's Mall
0.359375



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Tips

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Seeing Is Believing: How Visualization Simplifies IC DRC


Michael White
Senior Product Marketing Manager
Mentor Graphics Corp.

Tech Viewpoint

Verification Challenges
Require
Surgical Precision


Dr. Pranav Ashar
Chief Technical Officer
Real Intent, Inc.

Odd Parity

Summertime and the
Leavin’ Ain’t Easy


Mike Donlin
The Write Solution

Odd Parity Archive

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Reconfigurable Computing
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
.
Designer's Kiosk
Whitepapers & App Notes
Live and Archived Webcasts


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2010  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.4394531