May 9, 2003 -- At 0.13 microns and below, IC manufacturers are starting to see more defects that are not caught by traditional stuck-at-fault testing. Defects like high impedance metal, high impedance shorts, and crosstalk are not caught by traditional stuck at scan vectors. Instead they show up as timing failures that can only be caught by at-speed testing. Some ASIC vendors require at-speed test vectors and many others have plans to add that requirement.
In the past, at-speed testing was usually done by running a small number of functional vectors. This approach is time consuming and it produces poor coverage. DFT tools from EDA vendors can be used to generate at-speed scan vectors with good coverage.
These tools allow two types of at-speed testing: transition delay testing and path delay testing. Both work by generating scan patterns that can be scanned in at a slow speed. After a scan vector is scanned in, two or more capture clocks are applied at full speed and then the captured result is scanned out, usually at slow speed.
By Bob Neil. (Neil is a senior consulting engineer working for Paradigm Works.)
This brief introduction has been excerpted from the original copyrighted article.