February 27, 2006 -- With the advance of faster processors that require faster lines of communication, understanding and characterizing clock jitter has become more important. Jitter occurs in many different parts of digital applications. Jitter of data with respect to clock in synchronous protocols is one example; jitter of the signal itself in CDR (clock data recovery) applications is another.
While there are infinitely many types of jitter and several ways of measuring it, the choices available and the alternatives that the designer must consider can be narrowed significantly by defining his or her domain a bit more precisely.
The hardware design engineer, who is faced with seemingly incompatible definitions, throws in a towel, goes back to school, gets an MBA and joins the marketing department instead. Or (and this happens at least as often), the engineer simply designs the board without checking the jitter specs and hopes that it works.
The purpose of this article is to make such issues less complex and to remove this uncertainty by examining the jitter issues of the clock from which PLL-based processors derive timing as well as analyze the given clock's jitter with respect to an ideal clock, to the degree that the processorís tolerance requires.
Dealing with PLL Clock Jitter in Advanced Processor Designs: Part 2
By Boris Lerner and Aaron Lowenberger. (Lerner is senior DSP applications engineer and Lowenberger is a product engineer working on DSPs at Analog Devices, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Embedded website.
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