March 8, 2006 -- Without a detailed discussion of PLLs (which, in itself, has little to do with the subject at hand), we can just state that a PLL, being a phase locked loop, is linear in phase and, thus, is linear in jitter.
Although this statement is not as simple as it looks, it is correct and we’ll leave it at that. This is good news, because linear systems can be analyzed in terms of their frequency domain transfer function (i.e., frequency response).
Note that this transfer function is linear in jitter only. A PLL itself is certainly not linear as output with respect to input. Thus, the linear system discussion that follows looks at the transfer of jitter through the PLL only.
Dealing with PLL Clock Jitter in Advanced Processor Designs: Part 1
By Boris Lerner and Aaron Lowenberger. (Lerner is senior DSP applications engineer and Lowenberger is a product engineer working on DSPs at Analog Devices, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Embedded website.
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