May 8, 2006 -- Recent standards for assertions and newer verification methodologies have eased the designer's ability to create, implement and monitor assertions. The use of assertions in formal, simulation and acceleration/ emulation is accelerating as users see the tremendous benefits that can be gained by having assertions actively monitor their RTL code for errors.
With a complete assertion-based verification (ABV) methodology, designers write assertions as they develop the RTL. These assertions, along with automatically extracted assertions, are then verified using formal analysis on the individual blocks - sometimes months before simulation.
By Chris Komar and Michal Siwinski. (Komar is Incisive core competency senior technical leader and Siwinski is Incisive director at Cadence Design Systems, Inc.)
This brief introduction has been excerpted from the original copyrighted article.