May 22, 2006 -- To handle the increased size and complexity of designs, design and verification methodologies must operate at higher and higher levels of abstraction. These upward shifts in abstraction tend to occur about every decade or so. Today we are experiencing the graduation from RTL to transaction-level modeling (TLM).

Transaction-level models describe complex systems at a high level of abstraction, allowing designers to work through architectural issues before committing to low level-details of a complete implementation. In functional verification, transaction-based testbenches allow verification engineers to verify correct operation at the level at which the design was conceived. As the basis for advanced verification methodologies designed to tackle design complexity, TLM speeds up verification time scales and testbench execution times while enhancing reuse across levels of abstraction.

Of course, abstract designs must eventually be converted back to detailed designs in order to be implemented. Unlike the shift to RTL ten years ago accompanied by automated synthesis technology, TLM is the first shift upward in modeling abstraction that is not accompanied by a corresponding, automated path back down to the lower abstraction level. This leaves the transition down to RTL as essentially a manual process. Therefore, the only way to ensure the integrity of the transition is to put together a verification methodology that solves the problem of how to verify designs consistently at multiple levels of abstraction.

The new methodology must also make it easy for you to take advantage of functional coverage, constrained-random stimulus generation, assertions, and other advanced verification techniques, because they are the only way to ensure that the myriad corner cases of today’s complex designs are covered and that verification closure is attained with maximum confidence and efficiency.

The Mentor Graphics Advanced Verification Methodology (AVM) is the first, true, system-level-to-RTL verification methodology that allows you to apply leading-edge verification technologies to designs at multiple levels of abstraction, using multiple languages.

Open source and proven standards

Implemented in both SystemVerilog and SystemC, the AVM uses 100 percent LRM-compliant code. The communication mechanism between verification components in the AVM is based on the use of TLM interfaces as defined in the OSCI (Open SystemC Initiative) TLM-1.0 standard. By standardizing communication between components, you are free to focus on the component behavior to support constrained-random stimulus generation, functional coverage, score boarding, and more. Since all components utilize the same standard interfaces, the components themselves are highly reusable within and across multiple projects – another substantial productivity gain for the user. Productivity is further enhanced since the focus on TLM interfaces makes it easier to develop verification components at higher levels of abstraction, simplifying coding, debug, and test.

By relying on standard TLM interfaces, it is now possible to begin assembling a testbench around an early, transaction-level system model of a design. This testbench can be reused throughout the design refinement process simply by adding new components or adapters to convert the high-level transactions in the testbench to RTL behaviors connected to the device under test.

Figure 1. Reusing a transaction-level testbench with an RTL design.

The ingredients for advanced testbenches

The AVM provides a set of executable examples, libraries, and extensive documentation to help you develop modular, reusable testbenches more quickly. This forms the basis of an advanced testbench environment that combines transaction technology with traditional RTL verification techniques, providing a complete verification platform for verifying designs at any level of abstraction. These libraries solve many of the infrastructure-level problems typically encountered in setting up such environments, thereby improving your productivity by yielding functioning, reliable testbenches much faster.

In addition to the libraries of verification components, TLM interfaces, and other utilities, the AVM kit includes extensive runnable examples, in both SystemVerilog and SystemC, that progress incrementally from the basics of modularity and reusability up to realistic, domain-specific examples that illustrate how to assemble advanced coverage-driven testbenches. These examples and supporting libraries are delivered in open-source form, so the libraries and models provided can be used freely to help you get up and running on the next project.

The AVM includes extensive, book-form documentation (called the Verification Cookbook) that discusses the different concepts introduced in each example. This unique package of libraries, examples, and documentation provides an easy-to-use kit to get even the beginning verification engineer up and running quickly, while providing the features, modularity, and reusability that advanced verification engineers have come to expect.

All of the AVM libraries and examples are provided in open-source form, so you are free to use these to get up and running quickly. They can even add their own modifications on top of the source we provide. Not only is it based on the leading standard verification languages, but it is open-source and non-proprietary. Its code is freely available to anyone under an open-source Apache license. As a result, code is reusable and “future-proof.”

All of the AVM components are parameterized using the built-in parameterization features of SystemVerilog, so you are free to customize them as needed, while retaining full visibility into the operation of the components. This flexibility ultimately comes from the fact that SystemVerilog is defined to allow the free mixing of classes, modules, and interfaces, providing the full flexibility of this robust language to verification engineers of all levels of experience. The AVM takes full advantage of this flexibility to provide both the power that HVL users are used to and the ease-of-adoption required by HDL users, who may not be fully familiar or comfortable with object-oriented programming.

The AVM also provides implementations of TLM in both SystemVerilog and SystemC, so all of the concepts addressed by the AVM apply to the general development of testbenches and verification environments, regardless of the underlying language used for implementation. Obviously, each language has its strengths and weaknesses, but the AVM includes libraries and other infrastructures that take advantage of the strengths and supply additional functionality to address the weaknesses of each.

For example, the SystemC TLM implementation relies on the use of multiple inheritance to provide the flexibility, reuse, and protection discussed above. In SystemVerilog (which only supports single inheritance), standard Object-Oriented Programming techniques are used to implement the same interfaces and afford the same advantages of TLM as provided in SystemC. Conversely, SystemVerilog includes assertions and functional coverage directly in the language. In SystemC, a library of functional coverage components provides functionality similar to that of the SystemVerilog covergroup construct, affording SystemC users the same kinds of coverage capabilities. In SystemC, all components are themselves classes, so class/module duality is not an issue. SystemVerilog handles this issue deftly through its flexible use of either classes or modules for verification components.

Just as important, the AVM is language-neutral with respect to the design language used. The AVM testbench can be connected to designs in Verilog, VHDL, SystemVerilog, SystemC, or any combination thereof. In fact, the ability of the AVM to connect to VHDL designs means that, for the first time, VHDL users now have a standard, object-oriented testbench environment for applying the advanced verification features required for the functional verification of large, complex designs.

Modular, reusable models

By freely mixing classes and modules, the AVM has the advantage of being easy to connect directly to an RTL DUT, while retaining all the needed flexibility and configurability that HVL users have come to expect and demand. In addition to simplifying the DUT connections, the use of modules allows AVM-compliant components to contain assertions to check behaviors and collect coverage information, which can be communicated to the rest of the testbench via TLM.

The use of TLM, implemented in both SystemVerilog and SystemC, allows the exact same concepts to be applied to system-level architectural models written in SystemC as to RTL and gate-level models in SystemVerilog, Verilog, and VHDL. Regardless of the language used for either the testbench or the design, the AVM makes it much easier for users to define the topology of the test environment, leaving the verification engineers free to focus on the functionality of the specific components, such as stimulus generators, drivers, monitors, and scoreboards.

By Tom Fitzpatrick.

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings nearly two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. He has published multiple articles and technical papers about SystemVerilog, assertion-based verification, functional coverage, formal verification and other functional verification topics.