June 26,2006 -- As designers move to 65-nm technologies and below, the convergence of performance-driven design constraints and yield-driven manufacturing constraints intensifies the demand for new approaches for IC) physical design. At these geometries, more complex manufacturing effects dramatically impact the way engineers need to tune physical designs for optimal performance and yield. Besides addressing familiar speed and capacity concerns, advanced physical design requires an architectural approach that emphasizes quality of results, more effective convergence across a broader array of constraints, and significantly greater control by designers of the physical design process itself.
Faster routing of larger designs is not enough, and design convergence means much more than area, timing and power. Instead, designers need the ability to analyze routing more effectively, and incrementally improve both performance and yield with each physical design iteration.
As engineering teams move designs from high-level and detailed logic design to floorplanning and routing in physical design, they must work collaboratively to ensure that physical design maintains tight objectives for design performance, functionality and manufacturability. Accordingly, physical design and verification needs to work smoothly in the design flow, efficiently providing detailed results needed to ensure high quality results within tightening product schedules.
By Wilbur Luo and Craig Thompson. (Luo is the product marketing and application engineering director for the Project Catena advanced technology development group at Cadence Design Systems, Inc. and Thompson is senior product marketing manager for the Cadence Virtuoso custom IC design platform.)
This brief introduction has been excerpted from the original copyrighted article.
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