June 22, 2006 -- New SOC (system-on-chip) process technology brings with it some process, voltage, and temperature effects, as well as IR drop, which all impact timing closure. Designers can model the on-chip variation of these parameters without guardbanding and needlessly wasting design margin in increased area, increased power, or reduced performance. As core voltage drops below 1V in designs using 90-nm and smaller processes, IR-drop effects become more prominent. If they are not adequately addressed in the design flow, these IR drops can lead to setup-and-hold failures than can render the system inoperable.

The clock tree is one of the most sensitive parts of the design; thus, designers must carefully analyze it for on-chip-variation effects. Although you can quantify some of these effects using physical data, such as relative cell location and proximity to the power grid, you must statistically model other effects, such as transistor-threshold-voltage variation. Another issue that complicates timing analysis is RC-interconnect variation. Interconnect delay in deep-submicron processes can often dominate total delay; thus, you should model it as accurately as possible.

By Anis Jarrar and Kirk Taylor. (Jarrar is principal design engineer at Freescale Semiconductor, Inc. and Taylor is a principal design engineer at Freescale Semiconductor's Design Environment Organization.)