May 23, 2003 -- Traditionally chip designers have focused on how to satisfy the functional requirements of devices under time and design rule constraints, but have had no spare time to verify the function in-use-status. Package designers have focused on how to achieve low-cost design under the constraint of electrical, thermal and quality requirements. Only system designers have been conscious of the electrical performance of the system board, such as signal and power integrity, but the electrical model of the device is not always available from LSI suppliers.
SoC designs with data transfer rates beyond 500 Mbit/seconds fall in a gap between traditional design methods and the proposed chip-package-virtual board co-design method that this article will discuss.
By Tomoaki Isozaki and Hirofumi Nakajima. (Isozaki is with the Technology Foundation Development Division and Nakajima is with the Packaging and Testing Engineering Division of NEC Electronics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
