July 3, 2006 --Statistical static timing analysis (SSTA) offers a number of advantages over traditional corner based static timing analysis. Most notably, it provides a more realistic estimation of timing relative to actual silicon performance. Armed with a better answer, designers can focus their optimization efforts on the timing paths that have the biggest impact on overall performance and yield rather than paths that may fail only at extreme corners.
Meeting timing at the worst or best-case corner can be very challenging, lengthening design schedules and negatively impacting power consumption. With a large range of potential delay values, often with a difference of as much as 50 percent or more between the slow and fast process corners, it becomes harder to meet both setup times at the worst-case corner and hold times at the best-case corner.
Even if the performance goals are met, there is often an undesired impact on other design metrics, in particular power consumption, noise immunity and leakage. For example, to meet an aggressive performance target, optimization may deploy a higher ratio of low threshold cells that are faster but leakier. With statistical analysis, a better tradeoff between timing and other design metrics such as power, noise immunity can be achieved.
By Ken Tseng and Kelvin Le. (Tseng is chief technical officer at Altos Design Automation, Inc. and Le is member of technical staff at Extreme DA.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the eeDesign (EE Times EDA News) website.
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