August 7, 2006 -- While the trend to use more and more design intellectual property (IP) has considerably reduced design effort per gate, it has had the exact inverse effect on the functional verification effort. In fact, since integrating multiple design IP blocks is now the norm, verification has become the dominant task and source of risk in system-on-chip (SOC) projects. To cope with this challenge and contain these risks, design and verification teams recognize they need help.

The majority of design and verification teams today use verification IP (VIP) in one form or another. In fact, VIP is essential for any complex protocol or bus standard. Teams achieving the greatest success combine VIP use with a verification reuse strategy and a methodology that begins with an initial plan and goes all the way through to full verification closure.

Further contributing to verification IP's ascendance is the need to ensure compliance with the complex protocol's checklists. This is a major undertaking in itself and also must span the full verification process. VIP's end goal is to improve the verification process while reducing your verification project's risk profile. However, the decision as to which VIP to use has only gotten more complicated. Just as automobiles range from stripped down to high end models, several VIP classes now exist.

Since VIP is not created equal, it is critical to select not just any VIP, but the right VIP that balances your needs and resources against risks. When the wrong VIP is selected teams commonly face project delays and even outright project cancellations. This article will help you optimize VIP selection decisions. Furthermore, it will familiarize you with the various classes of VIP and the key issues to consider in your VIP selection.

By Pete Heller and Erez Kovshi. (Heller is Cadence's Product Line Manager for Verification IP and Kovshi is Cadence's Engineering Manager for PCI Express Verification IP.)