September 4, 2006 -- The larger and more complex that system-on-chip (SoC) designs grow, the more verification dominates the development process. In fact, effective design reuse puts even more pressure on the verification team to reduce their part of the schedule. The best solution to this dilemma is the adoption and deployment of a reuse-oriented, coverage-driven methodology that yields more efficient verification, while also increasing the likelihood of first-silicon success.
This is the last in a series of four articles outlining a reference verification methodology that meets these goals for both RTL and system-level verification. This methodology is enabled by the SystemVerilog hardware design and verification language standard and is documented in the Verification Methodology Manual (VMM) for SystemVerilog, a book jointly authored by ARM and Synopsys. This article focuses on ways to adopt the VMM methodology and deploy it quickly throughout an entire SoC project.
By Thomas Anderson, Janick Bergeron and Eduard Cerny, Alan Hunter and Andrew Nightingale. (Anderson is Director of Technical Marketing at Synopsys, Inc., Bergeron is a Scientist at Synopsys, Inc. and Cerny is a Principal Engineer, R&D, in the Verification Group at Synopsys, Inc.; Hunter is the Design Verification Methodology Program Manager at ARM, Ltd and Nightingale is a consultant engineer at ARM, Ltd.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the eeDesign (EE Times EDA News) website.
Read more about