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We Need "Enterprise" System-Level Solutions   Featured
Publication: EE Times EDA Designline
Contributor: Cadence Design Systems, Inc.
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November 20, 2006 -- To close the gaps in systems development across distributed design and verification teams it will become necessary to plan, design, and verify embedded software closer in-line with the way we currently design and verify hardware. In the past, embedded software development, or more specifically verification, has taken a back seat when compared to the hardware. In other words, as long as the perception remains that software can be relatively "easily" changed and firmware updates and patches can be made available, it will not be given the same level of focus, overall planning, or effort as the hardware.

This oversight or lack of planning in the area of hardware-software co-development has resulted in a situation where less investment and methodology development are budgeted for comprehensive "Enterprise" System-Level solutions. The increasing number of consumer products with embedded processors and embedded software, combined with time-to-market and system-level quality pressures, forced many system companies to re-think their design and verification strategy. The main area being overlooked includes hardware and software verification methods and tools that work together in a much more efficient, measured and managed way.

In order to make this leap into the world of hardware-software co-verification at the system level, companies will require new ways of thinking holistically. They will need to manage the various technologies, engines, verification IP, and methodologies for multi-specialist teams across the entire project (hardware and software). This broader awareness will address serious product lifecycle concerns and market pressures for those developing advanced SoCs and systems, which will in turn open up opportunities for EDA companies developing innovative enterprise-wide, system-level solutions.

By Ran Avinun. (Avinun is with Cadence Design Systems, Inc.)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

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Keywords: EE Times EDA Designline, Cadence Design Systems, verification, electronic system level design, ESL, EDA tools,
575/21022 11/20/2006 8874 641


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