February 12, 2007 -- Synopsys, Inc. today announced that that STMicroelectronics has deployed Synopsys Design Compiler topographical technology in its 90-nm and 65-nm ASIC design flow to expedite design time. STMicroelectronics is adopting Design Compiler topographical technology in its ASIC methodology to eliminate design iterations and streamline the overall design cycle for its internal design groups and for external customers.

Design Compiler topographical technology accurately predicts final design timing, power, testability and area results prior to actual physical implementation, giving front-end designers early visibility into layout results. In this way, both the customer and ASIC vendor can be assured that the netlist generated after synthesis will, in fact, achieve the desired performance.

"Topographical technology offers much-needed predictability for a convergent RTL-to-GDSII path. Front-end designers no longer have to wait for layout results to uncover critical design issues; they can identify and fix them up front. In turn, back-end teams receive a better netlist for physical implementation which is more likely to meet the desired performance," said Philippe Magarshack, Group Vice President, Central CAD and Design Solutions, Front-End Technology Manufacturing, at STMicroelectronics. "We are extremely pleased with the results we have seen with topographical technology on advanced ASIC designs and have incorporated it in both our 90-nanometer and 65-nanometer ASIC design flows. We encourage our internal and external ASIC customers to use it for all their synthesis needs to expedite the design process."